void USBDL_CLK_ON(kal_bool turn_on)
{
#if defined(DRV_UPLL_V1)
DRV_Reg(DRVPDN_CON0_CLR) |= DRVPDN_CON0_UPLL;
#elif defined(DRV_UPLL_V2)
/* hardware issue */
USB_PDNDisable(USB_PDN_OWNER_UPLL);
DRV_Reg(DRVPDN_CON0_CLR) |= DRVPDN_CON0_UPLL;
#elif defined(DRV_UPLL_V3)
/* select UPLL clock source from PLL */
DRV_Reg(PLL) |= 0x0040;
#elif defined(DRV_UPLL_V4)
DRV_Reg(DRVPDN_CON0) &= (~DRVPDN_CON0_PLL2);
/* disable USB clock from external clock */
DRV_Reg(CLK_CON) &= ~0x4000;
DRV_Reg(PLLSEL) |= 0x0008;
#elif defined(DRV_UPLL_V5)
/* This will be changed in 6238 E2 */
DRV_Reg(PLL) |= 0x0040;
#elif defined(DRV_USB_UPLL_MT50_SERIES)
if (SW_SEC_0 == INT_SW_SecVersion())
{
//DRV_Reg(0xA0010320) |= 0x0800;
PDN_CLR(PDN_USB_48M);
}
#endif
#if defined(MT6276)
DRV_Reg(0x61140280) |= 0x0080;
#endif
}
void USB_LOGGING_IRDBG_Trigger(void)
{
if (SW_SEC_0 == INT_SW_SecVersion())
{
IRQ_SetSWRegister(IRQ_IRDEBUG1_CODE);
}
}
/* USB LOGGING DSP LISR */
static void USB_LOGGING_DSP1_LISR(void)
{
IRQMask(IRQ_IRDEBUG1_CODE);
drv_active_hisr(DRV_USB_LOGGING_DSP1_HISR_ID);
#if defined(DRV_USB_LOGGING_MT50)
if (SW_SEC_0 == INT_SW_SecVersion())
{
IRQ_ResetSWRegister(IRQ_IRDEBUG1_CODE);
}
#endif
}
void UPLL_Enable(UPLL_OWNER owner)
{
#if (defined(DRV_UPLL_V1)||defined(DRV_UPLL_V2)||defined(DRV_UPLL_V3)||defined(DRV_UPLL_V4)||defined(DRV_UPLL_V5)||defined(DRV_UPLL_V6)||defined(DRV_UPLL_V7)||defined(DRV_UPLL_V8) || defined(DRV_USB_UPLL_MT50_SERIES))
kal_uint32 savedMask;
if(owner >= UPLL_OWNER_MAX)
EXT_ASSERT(0, (kal_uint32)owner, g_upll_owner, 0);
savedMask = SaveAndSetIRQMask();
if(g_upll_owner == 0)
{
#if defined(DRV_UPLL_V1)
USB_DRV_SetBits(DRVPDN_CON0_CLR , DRVPDN_CON0_UPLL);
#elif defined(DRV_UPLL_V2)
/* hardware issue */
USB_PDNDisable(USB_PDN_OWNER_UPLL);
USB_DRV_SetBits(DRVPDN_CON0_CLR , DRVPDN_CON0_UPLL);
#elif defined(DRV_UPLL_V3)
/* select UPLL clock source from PLL */
USB_DRV_SetBits(PLL , 0x0040);
#elif defined(DRV_UPLL_V4)
USB_DRV_ClearBits(DRVPDN_CON0 , DRVPDN_CON0_PLL2);
/* disable USB clock from external clock */
USB_DRV_ClearBits(CLK_CON , 0x4000);
USB_DRV_SetBits(PLLSEL , 0x0008);
#elif defined(DRV_UPLL_V5)
USB_DRV_SetBits(PLL , 0x0040);
#elif defined(DRV_UPLL_V6)
USB_DRV_SetBits(PDN_CON , 0x0010);
#elif defined(DRV_UPLL_V7)
USB_DRV_SetBits(UPLL_CON1, 0x0002);
#elif defined(DRV_UPLL_V8)
USB_DRV_SetBits(GPLL_CON0, 0x0080);
#elif defined(DRV_USB_UPLL_MT50_SERIES)
if (SW_SEC_0 == INT_SW_SecVersion())
{
PDN_CLR(PDN_USB_48M);
}
#endif
}
g_upll_owner |= 1<<(kal_uint32)owner;
RestoreIRQMask(savedMask);
#endif
}
/*
* FUNCTION
* ADC_GetData2Meta
*
* DESCRIPTION
* This function is called by META, and return the sum value.
*
* CALLS
*
* PARAMETERS
* sel : selection of input signal source(0-4)
* meacount: measure count
*
* RETURNS
* return the average value of ADC output
*
* GLOBALS AFFECTED
* None
*/
kal_uint32 ADC_GetData2Meta(kal_uint8 sel, kal_uint16 meacount)
{
#if defined(DRV_ADC_NOT_EXIST)
return 0;
#endif // #if defined(DRV_ADC_NOT_EXIST)
#ifndef DRV_ADC_NOT_EXIST
kal_uint32 index;
kal_uint32 sum=0;
#ifdef __MULTI_BOOT__
ADC_Factory_Boot_check();
#endif /*__MULTI_BOOT__*/
//DRVPDN_Disable(DRVPDN_CON2,DRVPDN_CON2_AUXADC,PDN_ADC);
//adc_pwrdown_disable();
#if defined(__DRV_ADC_SYNC_META__)
if(SW_SEC_0 == INT_SW_SecVersion()) //MT6250 E1
{
adcsche_adc_measure_en(KAL_TRUE);
adc_pwrdown_disable();
for(index=meacount;index!=0;index--)
{
sum += (kal_uint32)ADC_Sync_GetData(sel);
}
adc_pwrdown_enable();
}
else
{
for(index=meacount;index!=0;index--)
{
sum += (kal_uint32)ADC_GetData(sel);
}
}
#else
for(index=meacount;index!=0;index--)
{
sum += (kal_uint32)ADC_GetData(sel);
}
#endif
//DRVPDN_Enable(DRVPDN_CON2,DRVPDN_CON2_AUXADC,PDN_ADC);
//adc_pwrdown_enable();
return sum;
#endif // #ifndef DRV_ADC_NOT_EXIST
}
/*
* FUNCTION
* UPLL_Disable
*
* DESCRIPTION
* This function is to disable UPLL
*
* CALLS
* It is called to disable UPLL
*
* PARAMETERS
* owner = UPLL owner
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void UPLL_Disable(UPLL_OWNER owner)
{
#if (defined(DRV_UPLL_V1)||defined(DRV_UPLL_V2)||defined(DRV_UPLL_V3)||defined(DRV_UPLL_V4)||defined(DRV_UPLL_V5)||defined(DRV_UPLL_V6)||defined(DRV_UPLL_V7)||defined(DRV_UPLL_V8)|| defined(DRV_USB_UPLL_MT50_SERIES))
kal_uint32 savedMask;
if(owner >= UPLL_OWNER_MAX)
EXT_ASSERT(0, (kal_uint32)owner, g_upll_owner, 0);
savedMask = SaveAndSetIRQMask();
g_upll_owner &= ~(1<<(kal_uint32)owner);
if(g_upll_owner == 0)
{
#if defined(DRV_UPLL_V1)
USB_DRV_SetBits(DRVPDN_CON0_SET , DRVPDN_CON0_UPLL);
#elif defined(DRV_UPLL_V2)
/* hardware issue */
USB_PDNEnable(USB_PDN_OWNER_UPLL);
USB_DRV_SetBits(DRVPDN_CON0_SET , DRVPDN_CON0_UPLL);
#elif defined(DRV_UPLL_V3)
/* select UPLL clock source bypassed PLL */
USB_DRV_ClearBits(PLL , 0x0040);
#elif defined(DRV_UPLL_V4)
// DRV_Reg(DRVPDN_CON0) |= (DRVPDN_CON0_PLL2);
#elif defined(DRV_UPLL_V5)
#elif defined(DRV_UPLL_V6)
// DRV_Reg(PDN_CON)&= ~(0x0010); // set this bit will also clear MPLL
#elif defined(DRV_UPLL_V7)
// DRV_Reg(UPLL_CON1)&= ~(0x0002);
#elif defined(DRV_UPLL_V8)
USB_DRV_ClearBits(GPLL_CON0, 0x0080);
#elif defined(DRV_USB_UPLL_MT50_SERIES)
if (SW_SEC_0 == INT_SW_SecVersion())
{
PDN_SET(PDN_USB_48M);
}
#endif
}
RestoreIRQMask(savedMask);
#endif
}
void hif_init(void)
{
// Init structure.
memset(hif_internal_handle, 0, sizeof(hif_internal_handle));
#if defined (HIF0_CHANNEL_SUPPORT)
// Init HIF interrupr
IRQ_Register_LISR(IRQ_HIF_CODE, hif0_lisr, "HIF0 ISR");
IRQSensitivity(IRQ_HIF_CODE, LEVEL_SENSITIVE);
//hif_hisr_id[0] = kal_create_hisr("HIF0_HISR", 0, 1024, hif0_hisr, KAL_TRUE);
DRV_Register_HISR(DRV_HIF0_HISR_ID, hif0_hisr);
IRQUnmask(IRQ_HIF_CODE);
#endif
#if defined (HIF1_CHANNEL_SUPPORT)
IRQ_Register_LISR(IRQ_HIF_1_CODE, hif1_lisr, "HIF1 ISR");
IRQSensitivity(IRQ_HIF_1_CODE, LEVEL_SENSITIVE);
//hif_hisr_id[1] = kal_create_hisr("HIF1_HISR", 0, 1024, hif1_hisr, KAL_TRUE);
DRV_Register_HISR(DRV_HIF1_HISR_ID, hif1_hisr);
IRQUnmask(IRQ_HIF_1_CODE);
#endif
/* DMA initialization */
#if defined (HIF0_CHANNEL_SUPPORT)
hif_sysdma_id[0] = DMA_GetChannel(DMA_HIF0);
hif_dma_menu[0].TMOD.burst_mode = KAL_FALSE;
hif_dma_menu[0].master = DMA_HIF0;
hif_dma_menu[0].addr = 0;
#endif
#if defined (HIF1_CHANNEL_SUPPORT)
hif_sysdma_id[1] = DMA_GetChannel(DMA_HIF1);
hif_dma_menu[1].TMOD.burst_mode = KAL_FALSE;
hif_dma_menu[1].master = DMA_HIF1;
hif_dma_menu[1].addr = 0;
#endif
// Configure DMA
//hif_dma_input.size = DMA_SHORT;
hif_dma_input[0].count = 0;
hif_dma_input[0].callback = NULL;
hif_dma_input[1].count = 0;
hif_dma_input[1].callback = NULL;
//hif_dma_input.menu = (void*) &hif_dma_menu;
//define ECO solution for MT6256E4,MT6575E2, MT6255E2 or MTK later chips
#if defined(MT6255) || defined(MT6256)//MT6255 and MT6256 support query chip version
chip_version = INT_SW_SecVersion(); //Query chip version
#endif
#if defined(__AST_TL1_TDD__) //HIF ECO only support for TDD project
#if defined(MT6575_S01)
hif_eco_support = KAL_FALSE;
#elif defined(MT6752)
hif_eco_support = KAL_TRUE;
#elif defined(MT6255) //MT6255E2 support HIF ECO
if(SW_SEC_0 != chip_version)
{
hif_eco_support = KAL_TRUE;
}
#elif defined(MT6256) //MT6256E4,MT6256E5 support HIF ECO
if(SW_SEC_1 == chip_version) //SW_SEC_0: MT6256E2,E3,E4, SW_SEC_1: MT6256E5
{
hif_eco_support = KAL_TRUE;
}
#endif
#endif
hif_events = kal_create_event_group("HIFDrv");
}
