/*---------------------------------------------------------------------------* * Requirement routines: *---------------------------------------------------------------------------*/ void LPC1768_I2S_Require(const T_LPC1768_I2S_Settings *aSettings) { static const T_LPC1768_IOCON_ConfigList pinsRX_SCK[] = { {GPIO_P0_4, IOCON_D_DEFAULT(1)}, {GPIO_P0_23, IOCON_A_DEFAULT(2)}, }; static const T_LPC1768_IOCON_ConfigList pinsRX_SDA[] = { {GPIO_P0_6, IOCON_D_DEFAULT(1)}, {GPIO_P0_25, IOCON_D_DEFAULT(2)}, }; static const T_LPC1768_IOCON_ConfigList pinsRX_WS[] = { {GPIO_P0_5, IOCON_D_DEFAULT(1)}, {GPIO_P0_24, IOCON_A_DEFAULT(2)}, }; static const T_LPC1768_IOCON_ConfigList pinsRX_MCLK[] = { {GPIO_P4_28, IOCON_D_DEFAULT(2)}, }; static const T_LPC1768_IOCON_ConfigList pinsTX_SCK[] = { {GPIO_P2_11, IOCON_D_DEFAULT(3)}, {GPIO_P0_7, IOCON_W_DEFAULT(1)}, }; static const T_LPC1768_IOCON_ConfigList pinsTX_SDA[] = { {GPIO_P2_13, IOCON_D_DEFAULT(3)}, {GPIO_P0_9, IOCON_W_DEFAULT(1)}, }; static const T_LPC1768_IOCON_ConfigList pinsTX_WS[] = { {GPIO_P2_12, IOCON_D_DEFAULT(3)}, {GPIO_P0_8, IOCON_W_DEFAULT(1)}, }; static const T_LPC1768_IOCON_ConfigList pinsTX_MCLK[] = { {GPIO_P4_29, IOCON_D_DEFAULT(2)}, }; HAL_DEVICE_REQUIRE_ONCE(); // Register I2S Bus drivers HALInterfaceRegister("I2S", (T_halInterface *)&G_LPC1768_I2S_Interface, 0, 0); LPC1768_IOCON_ConfigPinOrNone(aSettings->iRX_SCK, pinsRX_SCK, ARRAY_COUNT(pinsRX_SCK)); LPC1768_IOCON_ConfigPinOrNone(aSettings->iRX_SDA, pinsRX_SDA, ARRAY_COUNT(pinsRX_SDA)); LPC1768_IOCON_ConfigPinOrNone(aSettings->iRX_WS, pinsRX_WS, ARRAY_COUNT(pinsRX_WS)); LPC1768_IOCON_ConfigPinOrNone(aSettings->iRX_MCLK, pinsRX_MCLK, ARRAY_COUNT(pinsRX_MCLK)); LPC1768_IOCON_ConfigPinOrNone(aSettings->iTX_SCK, pinsTX_SCK, ARRAY_COUNT(pinsTX_SCK)); LPC1768_IOCON_ConfigPinOrNone(aSettings->iTX_SDA, pinsTX_SDA, ARRAY_COUNT(pinsTX_SDA)); LPC1768_IOCON_ConfigPinOrNone(aSettings->iTX_WS, pinsTX_WS, ARRAY_COUNT(pinsTX_WS)); LPC1768_IOCON_ConfigPinOrNone(aSettings->iTX_MCLK, pinsTX_MCLK, ARRAY_COUNT(pinsTX_MCLK)); }
void LPC17xx_40xx_Timer3_Require(const T_LPC17xx_40xx_Timer_Settings *aSettings) { static const T_LPC17xx_40xx_IOCON_ConfigList pinsCAP0[] = { {GPIO_P1_10, IOCON_D_DEFAULT(3)}, // T3_CAP0 {GPIO_P2_22, IOCON_D_DEFAULT(3)}, // T3_CAP0 {GPIO_P0_23, IOCON_W_DEFAULT(3)}, // T3_CAP0 }; static const T_LPC17xx_40xx_IOCON_ConfigList pinsCAP1[] = { {GPIO_P1_0, IOCON_D_DEFAULT(3)}, // T3_CAP1 {GPIO_P2_23, IOCON_D_DEFAULT(3)}, // T3_CAP1 {GPIO_P0_24, IOCON_W_DEFAULT(3)}, // T3_CAP1 }; static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT0[] = { {GPIO_P0_10, IOCON_D_DEFAULT(3)}, // T3_MAT0 {GPIO_P1_9, IOCON_D_DEFAULT(3)}, // T3_MAT0 {GPIO_P2_26, IOCON_D_DEFAULT(3)}, // T3_MAT0 }; static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT1[] = { {GPIO_P0_11, IOCON_D_DEFAULT(3)}, // T3_MAT1 {GPIO_P1_8, IOCON_D_DEFAULT(3)}, // T3_MAT1 {GPIO_P2_27, IOCON_D_DEFAULT(3)}, // T3_MAT1 }; static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT2[] = { {GPIO_P1_4, IOCON_D_DEFAULT(3)}, // T3_MAT2 {GPIO_P2_30, IOCON_D_DEFAULT(3)}, // T3_MAT2 {GPIO_P5_2, IOCON_I_DEFAULT(3)}, // T3_MAT2 }; static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT3[] = { {GPIO_P1_1, IOCON_D_DEFAULT(3)}, // T3_MAT3 {GPIO_P2_31, IOCON_D_DEFAULT(3)}, // T3_MAT3 {GPIO_P5_4, IOCON_D_DEFAULT(3)}, // T3_MAT3 }; HAL_DEVICE_REQUIRE_ONCE(); // Register Timer3 HALInterfaceRegister("Timer3", (T_halInterface *)&LPC17xx_40xx_Timer3_Interface, 0, 0); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCAP[0], pinsCAP0, ARRAY_COUNT(pinsCAP0)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCAP[1], pinsCAP1, ARRAY_COUNT(pinsCAP1)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[0], pinsMAT0, ARRAY_COUNT(pinsMAT0)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[1], pinsMAT1, ARRAY_COUNT(pinsMAT1)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[2], pinsMAT2, ARRAY_COUNT(pinsMAT2)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[2], pinsMAT3, ARRAY_COUNT(pinsMAT3)); }
void LPC17xx_40xx_Timer2_Require(const T_LPC17xx_40xx_Timer_Settings *aSettings) { static const T_LPC17xx_40xx_IOCON_ConfigList pinsCAP0[] = { {GPIO_P0_4, IOCON_D_DEFAULT(3)}, // T2_CAP0 {GPIO_P1_14, IOCON_D_DEFAULT(3)}, // T2_CAP0 {GPIO_P2_6, IOCON_D_DEFAULT(3)}, // T2_CAP0 {GPIO_P2_14, IOCON_D_DEFAULT(3)}, // T2_CAP0 }; static const T_LPC17xx_40xx_IOCON_ConfigList pinsCAP1[] = { {GPIO_P0_5, IOCON_D_DEFAULT(3)}, // T2_CAP1 {GPIO_P2_15, IOCON_D_DEFAULT(3)}, // T2_CAP1 }; static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT0[] = { {GPIO_P0_6, IOCON_D_DEFAULT(3)}, // T2_MAT0 {GPIO_P2_5, IOCON_D_DEFAULT(3)}, // T2_MAT0 {GPIO_P4_28, IOCON_D_DEFAULT(3)}, // T2_MAT0 }; static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT1[] = { {GPIO_P0_7, IOCON_W_DEFAULT(3)}, // T2_MAT1 {GPIO_P2_4, IOCON_D_DEFAULT(3)}, // T2_MAT1 {GPIO_P4_29, IOCON_D_DEFAULT(3)}, // T2_MAT1 }; static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT2[] = { {GPIO_P0_8, IOCON_W_DEFAULT(3)}, // T2_MAT2 {GPIO_P2_3, IOCON_D_DEFAULT(3)}, // T2_MAT2 {GPIO_P5_0, IOCON_D_DEFAULT(3)}, // T2_MAT2 }; static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT3[] = { {GPIO_P0_9, IOCON_W_DEFAULT(3)}, // T2_MAT3 {GPIO_P2_2, IOCON_D_DEFAULT(3)}, // T2_MAT3 {GPIO_P5_1, IOCON_D_DEFAULT(3)}, // T2_MAT3 }; HAL_DEVICE_REQUIRE_ONCE(); // Register Timer2 HALInterfaceRegister("Timer2", (T_halInterface *)&LPC17xx_40xx_Timer2_Interface, 0, 0); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCAP[0], pinsCAP0, ARRAY_COUNT(pinsCAP0)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCAP[1], pinsCAP1, ARRAY_COUNT(pinsCAP1)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[0], pinsMAT0, ARRAY_COUNT(pinsMAT0)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[1], pinsMAT1, ARRAY_COUNT(pinsMAT1)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[2], pinsMAT2, ARRAY_COUNT(pinsMAT2)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[2], pinsMAT3, ARRAY_COUNT(pinsMAT3)); }
void LPC17xx_40xx_SSP1_Require( T_uezGPIOPortPin aPinSCK1, T_uezGPIOPortPin aPinMISO1, T_uezGPIOPortPin aPinMOSI1, T_uezGPIOPortPin aPinSSEL1) { static const T_LPC17xx_40xx_IOCON_ConfigList sck1[] = { {GPIO_P0_7, IOCON_W_DEFAULT(2)}, {GPIO_P1_19, IOCON_D_DEFAULT(5)}, {GPIO_P1_31, IOCON_A_DEFAULT(2)}, {GPIO_P4_20, IOCON_D_DEFAULT(3)}, }; static const T_LPC17xx_40xx_IOCON_ConfigList ssel1[] = { {GPIO_P0_6, IOCON_D_DEFAULT(2)}, {GPIO_P0_14, IOCON_D_DEFAULT(2)}, {GPIO_P4_21, IOCON_D_DEFAULT(3)}, }; static const T_LPC17xx_40xx_IOCON_ConfigList miso1[] = { {GPIO_P0_8, IOCON_W_DEFAULT(2)}, {GPIO_P0_12, IOCON_A_DEFAULT(2)}, {GPIO_P1_18, IOCON_D_DEFAULT(5)}, {GPIO_P4_22, IOCON_D_DEFAULT(3)}, }; static const T_LPC17xx_40xx_IOCON_ConfigList mosi1[] = { {GPIO_P0_9, IOCON_W_DEFAULT(2)}, {GPIO_P0_13, IOCON_A_DEFAULT(2)}, {GPIO_P1_22, IOCON_D_DEFAULT(5)}, {GPIO_P4_23, IOCON_D_DEFAULT(3)}, }; HAL_DEVICE_REQUIRE_ONCE(); // Register SSP1 HALInterfaceRegister("SSP1", (T_halInterface *)&SSP_LPC17xx_40xx_Port1_Interface, 0, 0); LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinSCK1, sck1, ARRAY_COUNT(sck1)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinSSEL1, ssel1, ARRAY_COUNT(ssel1)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinMISO1, miso1, ARRAY_COUNT(miso1)); LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinMOSI1, mosi1, ARRAY_COUNT(mosi1)); LPC17xx_40xxPowerOn(1<<10); // Setup interrupt, but do not enable InterruptRegister(SSP1_IRQn, ISSP1IRQ, INTERRUPT_PRIORITY_HIGH, "SSP1"); InterruptDisable(SSP1_IRQn); }