static void setup_mmconfig(void) { uint32_t reg; /* Set up the MMCONF range. The register lives in the BUNIT. The * IO variant of the config access needs to be used initially to * properly configure as the IOSF access registers live in PCI * config space. */ reg = 0; /* Clear the extended register. */ pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 1; pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); }
/* This sequence signals the PUNIT to start running. */ void punit_init(void) { uint32_t reg; uint8_t rid; const struct device *dev; const struct soc_intel_baytrail_config *cfg = NULL; rid = pci_read_config8(IOSF_PCI_DEV, REVID); dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)); if (dev) cfg = dev->chip_info; reg = iosf_punit_read(SB_BIOS_CONFIG); /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; /* Configure VR low power mode for C0 and above. */ if (rid >= RID_C_STEPPING_START && cfg != NULL && (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) { printk(BIOS_DEBUG, "Enabling VR PS2 mode: "); if (cfg->vnn_ps2_enable) { reg |= SB_BIOS_CONFIG_PS2_EN_VNN; printk(BIOS_DEBUG, "VNN "); } if (cfg->vcc_ps2_enable) { reg |= SB_BIOS_CONFIG_PS2_EN_VCC; printk(BIOS_DEBUG, "VCC "); } printk(BIOS_DEBUG, "\n"); } iosf_punit_write(SB_BIOS_CONFIG, reg); /* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE; pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(BIOS_RESET_CPL) | IOSF_BYTE_EN_0; pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); }
uint32_t iosf_dunit_ch1_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | IOSF_PORT(IOSF_PORT_DUNIT_CH1); return iosf_read_port(cr, reg); }