int
arm_get_next_irq(int last_irq)
{
uint32_t pending;
int32_t irq = last_irq + 1;
/* Sanity check */
if (irq < 0)
irq = 0;
/* TODO: should we mask last_irq? */
pending = intc_read_4(INTC_PENDING_BASIC);
while (irq < BANK1_START) {
if (pending & (1 << irq))
return irq;
irq++;
}
pending = intc_read_4(INTC_PENDING_BANK1);
while (irq < BANK2_START) {
if (pending & (1 << IRQ_BANK1(irq)))
return irq;
irq++;
}
pending = intc_read_4(INTC_PENDING_BANK2);
while (irq <= BANK2_END) {
if (pending & (1 << IRQ_BANK2(irq)))
return irq;
irq++;
}
return (-1);
}
void
arm_unmask_irq(uintptr_t nb)
{
dprintf("%s: %d\n", __func__, nb);
if (IS_IRQ_BASIC(nb))
intc_write_4(INTC_ENABLE_BASIC, (1 << nb));
else if (IS_IRQ_BANK1(nb))
intc_write_4(INTC_ENABLE_BANK1, (1 << IRQ_BANK1(nb)));
else if (IS_IRQ_BANK2(nb))
intc_write_4(INTC_ENABLE_BANK2, (1 << IRQ_BANK2(nb)));
else
printf("arm_mask_irq: Invalid IRQ number: %d\n", nb);
}
static int
bcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref)
{
struct bcm_intc_irqsrc *bii;
int error;
uint32_t irq;
const char *name;
name = device_get_nameunit(sc->sc_dev);
for (irq = 0; irq < BCM_INTC_NIRQS; irq++) {
bii = &sc->intc_isrcs[irq];
bii->bii_irq = irq;
if (IS_IRQ_BASIC(irq)) {
bii->bii_disable_reg = INTC_DISABLE_BASIC;
bii->bii_enable_reg = INTC_ENABLE_BASIC;
bii->bii_mask = 1 << irq;
} else if (IS_IRQ_BANK1(irq)) {
bii->bii_disable_reg = INTC_DISABLE_BANK1;
bii->bii_enable_reg = INTC_ENABLE_BANK1;
bii->bii_mask = 1 << IRQ_BANK1(irq);
} else if (IS_IRQ_BANK2(irq)) {
bii->bii_disable_reg = INTC_DISABLE_BANK2;
bii->bii_enable_reg = INTC_ENABLE_BANK2;
bii->bii_mask = 1 << IRQ_BANK2(irq);
} else
return (ENXIO);
error = intr_isrc_register(&bii->bii_isrc, sc->sc_dev, 0,
"%s,%u", name, irq);
if (error != 0)
return (error);
}
if (intr_pic_register(sc->sc_dev, xref) == NULL)
return (ENXIO);
return (0);
}