static void IRQ_SoftInt_Clear(void)
{
*(volatile UInt32*)(KONA_BINTC_BASE_ADDR + BINTC_ISWIR0_CLR_OFFSET) =
1<<IRQ_TO_BMIRQ(DSP_OTOAINT);
*(volatile UInt32*)(KONA_BINTC_BASE_ADDR + BINTC_ICR0_OFFSET) =
1<<IRQ_TO_BMIRQ(DSP_OTOAINT);
return;
}
static UInt32 IRQ_EnableRIPInt(void)
{
chal_bmintc_enable_interrupt(dsp_drv.h, BINTC_OUT_DEST_AP2DSP,
(UInt32) IRQ_TO_BMIRQ(AP_RIP_IRQ));
return 1;
}
static void IRQ_EnableRIPInt(void)
{
unsigned int x;
void __iomem *chipreg_base = (void __iomem *)(KONA_CHIPREG_VA);
void __iomem *base = (void __iomem *)(KONA_BINTC_BASE_ADDR);
if (vp_shared_mem->shared_dsp_support_chip_reg_ap_int) {
vp_shared_mem->shared_ap_support_chip_reg_ap_int = 1;
aTrace(LOG_AUDIO_DSP, "\n\r\t*IRQ_EnableRIPInt: New Int*\n\r");
writel((1<<CHIPREG_OUTPUT12),
(base + BINTC_IMR0_15_SET_OFFSET));
//Programming Ap2DSP as wakeup event for power manager
writel((1<<CHIPREG_OUTPUT12),(base + BINTC_IMR0_9_SET_OFFSET));
x=readl(chipreg_base + CHIPREG_MDM_SW_INTR_SEL_OFFSET);
x|=(1<<CHIPREG_OUTPUT12);
writel(x,(chipreg_base + CHIPREG_MDM_SW_INTR_SEL_OFFSET));
} else {
aTrace(LOG_AUDIO_DSP, "\n\r\t*IRQ_EnableRIPInt: Old Int*\n\r");
vp_shared_mem->shared_ap_support_chip_reg_ap_int = 0;
*(volatile UInt32*)(KONA_BINTC_BASE_ADDR +
BINTC_IMR1_0_SET_OFFSET +
BINTC_OUT_DEST_AP2DSP*BMREG_BLOCK_SIZE) =
1<<(IRQ_TO_BMIRQ(AP_RIP_IRQ)-32);
}
printk(KERN_INFO "\n\r\t*IRQ_EnableRIPInt "
" shared_dsp_support_chip_reg_ap_int = %x*\n\r"
"\n\r\t* shared_ap_support_chip_reg_ap_int = %x*\n\r",
vp_shared_mem->shared_dsp_support_chip_reg_ap_int,
vp_shared_mem->shared_ap_support_chip_reg_ap_int);
return;
}
void intc_trigger_softirq(unsigned int irq)
{
void __iomem *chipreg_base = (void __iomem *)(KONA_CHIPREG_VA);
unsigned int birq = IRQ_TO_BMIRQ(IRQ_IPC_A2C);
/* convert to BModem IRQ */
unsigned long flags;
unsigned int ReadData=0;;
/* removed printouts */
/* printk("intc_trigger_softirq\n"); */
spin_lock_irqsave(&intc_lock, flags);
// This SEL code is for safety only, bits in this register are shared for some other operations
//This is additional read and write to register and may cause extra dealy.
// if the code stability is proven , we can remove this code below 3 lines INTR_SEL.
ReadData=readl(chipreg_base + CHIPREG_MDM_SW_INTR_SEL_OFFSET );
ReadData|=(1<<birq);
writel(ReadData, chipreg_base + CHIPREG_MDM_SW_INTR_SEL_OFFSET );
writel((1<<birq), chipreg_base + CHIPREG_MDM_SW_INTR_SET_OFFSET );
spin_unlock_irqrestore(&intc_lock, flags);
}
static void IRQ_Enable_BModem_Interrupt(void)
{
*(volatile UInt32*)(KONA_BINTC_BASE_ADDR + BINTC_IMR0_0_SET_OFFSET +
BINTC_OUT_DEST_6*BMREG_BLOCK_SIZE) =
1<<IRQ_TO_BMIRQ(DSP_OTOAINT);
return;
}
static irqreturn_t ipcs_interrupt(int irq, void *dev_id)
{
void __iomem *base = (void __iomem *)(KONA_BINTC_BASE_ADDR);
int birq = IRQ_TO_BMIRQ(IRQ_IPC_C2A_BINTC); //55;
/* Clear the interrupt */
if (birq >= 32)
writel(1 << (birq - 32),
base + BINTC_ISWIR1_CLR_OFFSET /*0x34 */ );
else
writel(1 << (birq), base + BINTC_ISWIR0_CLR_OFFSET /*0x24 */ );
#ifdef CONFIG_HAS_WAKELOCK
wake_lock(&ipc_wake_lock);
#endif
tasklet_schedule(&g_ipc_info.intr_tasklet);
return IRQ_HANDLED;
}
static void IRQ_TriggerRIPInt(void)
{
void __iomem *chipreg_base = (void __iomem *)(KONA_CHIPREG_VA);
/* Forcing new interrupt in case DSP woke up after the Interrupt */
/* was enabled */
if ((vp_shared_mem->shared_ap_support_chip_reg_ap_int == 0) &&
(vp_shared_mem->shared_dsp_support_chip_reg_ap_int == 1))
IRQ_EnableRIPInt();
if (vp_shared_mem->shared_ap_support_chip_reg_ap_int) {
aTrace(LOG_AUDIO_DSP, "\n\r\t*IRQ_TriggerRIPInt: New Int*\n\r");
writel((1<<CHIPREG_OUTPUT12), (chipreg_base +
CHIPREG_MDM_SW_INTR_SET_OFFSET));
} else {
aTrace(LOG_AUDIO_DSP, "\n\r\t*IRQ_TriggerRIPInt: Old Int*\n\r");
*(volatile UInt32*)(KONA_BINTC_BASE_ADDR +
BINTC_ISWIR1_OFFSET) = 1<<(IRQ_TO_BMIRQ(AP_RIP_IRQ)-32);
}
return;
}
static void IRQ_SoftInt_Clear(InterruptId_t Id)
{
chal_bmintc_clear_soft_int(dsp_drv.h, IRQ_TO_BMIRQ(Id));
chal_bmintc_clear_interrupt(dsp_drv.h, IRQ_TO_BMIRQ(Id));
}
static void IRQ_TriggerRIPInt(void)
{
chal_bmintc_set_soft_int(dsp_drv.h, (UInt32) IRQ_TO_BMIRQ(AP_RIP_IRQ));
}
static void IRQ_Enable_BModem_Interrupt(InterruptId_t Id, UInt32 DstID)
{
chal_bmintc_enable_interrupt(dsp_drv.h, DstID,
(UInt32) IRQ_TO_BMIRQ(Id));
return;
}
