void ir_reg_irda_set_carrier_mode(void) { IR_WRITE_CR10(IR_CR10_SIR_RX_MODE); IR_WRITE_CR15(IR_CR15_OPT_IO_A_CNN_ENA); IR_WRITE_CR11(IR_CR11_OPTINPUT_REV); IR_WRITE_CR0(IR_CR0_TX_RESET | IR_CR0_RX_RESET | IR_CR0_CAREER_RESET); }
void ir_reg_irda_int_clear(void) { volatile uint16 w_dmy; IR_WRITE_CR3(IR_CR3_TXRX_DISENA); IR_WRITE_CR22(IR_CR22_UART_DISENA); IR_WRITE_CR20(IR_CR20_RX_CRC_ERR_MSK | IR_CR20_RX_OVERRUN_ERR_MSK | IR_CR20_RX_STOP_ERR_MSK | IR_CR20_RX_PRTY_ERR_MSK | IR_CR20_RX_END_MSK | IR_CR20_TX_BUF_SP_ENA_MSK | IR_CR20_TX_BUF_SP_MSK | IR_CR20_TX_END_MSK); IR_WRITE_CR2(IR_CR2_RX_START_MSK | IR_CR2_RX_OVERRUN_ERR_MSK | IR_CR2_RX_FLM_ERR_MSK | IR_CR2_RX_END_MSK | IR_CR2_TIMER_INTRPT_MSK | IR_CR2_TX_UNDERRUN_ERR_MSK | IR_CR2_TX_END_MSK); IR_WRITE_CR0(IR_CR0_TIMER_RESET); w_dmy = IR_READ_SR3; w_dmy = IR_READ_SR18; }
void ir_reg_irdadrv_fir_set_led(void) { unsigned long spin_lock_flags; struct timespec tu; register uint16 w_dmy; register uint16 w_dmy2 = IR_CR15_SD_TERM | IR_CR15_IRTX_AB_OUTPUT | IR_CR15_IRTX_A_OUTDATA; register uint16 w_dmy3 = IR_CR15_IRTX_AB_OUTPUT | IR_CR15_IRTX_A_OUTDATA; IR_WRITE_CR0(IR_CR0_SYSTEM_RESET | IR_CR0_CAREER_RESET); w_dmy = IR_READ_SR14; spin_lock_irqsave(&Irreg_spin_lock, spin_lock_flags); *(volatile uint16*)IR_REG_CR15 = w_dmy2; *(volatile uint16*)IR_REG_CR14 = w_dmy2; *(volatile uint16*)IR_REG_CR15 = w_dmy3; w_dmy = IR_READ_SR14; IR_WRITE_CR15(IR_CR15_OPT_IO_A_CNN_ENA); spin_unlock_irqrestore(&Irreg_spin_lock, spin_lock_flags); tu.tv_sec = 0; tu.tv_nsec = IR_SD_RECOVERY_WAIT_NSEC; hrtimer_nanosleep(&tu, NULL, HRTIMER_MODE_REL, CLOCK_MONOTONIC); }
static void ir_reg_irdacc_dis(void) { IR_WRITE_CR0(IR_CR0_SYSTEM_RESET | IR_CR0_CAREER_RESET); IR_WRITE_CR22(IR_CR22_UART_DISENA); IR_WRITE_CR26(IR_CR26_FIFO_RESET); IR_WRITE_CR27(IR_CR27_FIFO_INIT_MODE); IRM_GLT_WRITE_REG(IR_GLT_REG_IRDASYS, IR_GLT_REG_CLR); }
void ir_reg_irda_carrier_timer_init(uint16 tm) { uint16 a_sr; a_sr = IR_READ_SR11; IR_WRITE_CR11(a_sr & ~IR_CR11_TIMER_CYCYE_CHG); IR_WRITE_CR12(tm); IR_WRITE_CR0(IR_CR0_TIMER_RESET); a_sr = IR_READ_SR2; IR_WRITE_CR2(a_sr & ~IR_CR2_TIMER_INTRPT_MSK); }
static void ir_reg_irdacc_ena(void) { register uint16 w_dmy = IR_CR15_OPT_IO_A_CNN_ENA; IRM_GLT_WRITE_REG(IR_GLT_REG_IRDADIV, IR_GLT_IRDADIV); IRM_GLT_WRITE_REG(IR_GLT_REG_IRDASYS, IR_GLT_IRDASYS); IR_WRITE_CR0(IR_CR0_SYSTEM_RESET | IR_CR0_CAREER_RESET); *(volatile uint16*)IR_REG_CR14 = w_dmy; w_dmy = IR_READ_SR14; }
TYPE_IR_REG_RESULT ir_reg_irda_carrier_chk(void) { uint16 a_sr1; TYPE_IR_REG_RESULT w_ret; a_sr1 = IR_READ_SR1; if ((a_sr1 & IR_SR1_CRRIA_RACH) != IR_SR_CLEAR) { IR_WRITE_CR0(IR_CR0_CAREER_RESET); w_ret = IR_REG_RESULT_SUCCESS; } else { w_ret = IR_REG_RESULT_FAIL; } return (w_ret); }
void ir_reg_irda_sir_set_rx_adr_match(void) { IR_WRITE_CR15(IR_CR15_OPT_IO_A_CNN_ENA); IR_WRITE_CR0(IR_CR0_RECEIVE_CNT_SEL); IR_WRITE_CR20(IR_CR20_TX_BUF_SP_ENA_MSK | IR_CR20_TX_BUF_SP_MSK | IR_CR20_TX_END_MSK); IR_WRITE_CR10(IR_CR10_SIR_RX_MODE); IR_WRITE_CR11(IR_CR11_OPTINPUT_REV); IR_WRITE_CR26(IR_CR26_FIFO_RESET); IR_WRITE_CR27(IR_CR27_FIFO_RX_MODE); IR_WRITE_CR3(IR_CR3_ADR_MCH_ENA); IR_WRITE_CR22(IR_CR22_UART_RX_ENA); }
void ir_reg_irda_fir_set_rx_adr_match(void) { IR_WRITE_CR15(IR_CR15_CONTINU_PKT_RX_ENA | IR_CR15_OPT_IO_A_CNN_ENA); IR_WRITE_CR0(IR_CR0_RECEIVE_CNT_SEL); IR_WRITE_CR1(IR_CR1_DEFSET); IR_WRITE_CR2(IR_CR2_RX_START_MSK | IR_CR2_TIMER_INTRPT_MSK | IR_CR2_TX_UNDERRUN_ERR_MSK | IR_CR2_TX_END_MSK); IR_WRITE_CR10(IR_CR10_FIR_RX_MODE); IR_WRITE_CR11(IR_CR11_OPTINPUT_REV); IR_WRITE_CR26(IR_CR26_FIFO_RESET); IR_WRITE_CR27(IR_CR27_FIFO_4M_RX_MODE); IR_WRITE_CR3(IR_CR3_RX_ENA | IR_CR3_RX_CRC_ENA | IR_CR3_ADR_MCH_ENA); }
void ir_reg_irda_sir_set_tx(TYPE_IR_SEND_KIND a_kind) { IR_WRITE_CR15(IR_CR15_OPT_IO_A_CNN_ENA); IR_WRITE_CR0(IR_CR0_SEND_CNT_SEL); IR_WRITE_CR20(IR_CR20_RX_CRC_ERR_MSK | IR_CR20_RX_OVERRUN_ERR_MSK | IR_CR20_RX_STOP_ERR_MSK | IR_CR20_RX_PRTY_ERR_MSK | IR_CR20_RX_END_MSK | IR_CR20_TX_BUF_SP_ENA_MSK | IR_CR20_TX_BUF_SP_MSK); IR_WRITE_CR10(IR_CR10_SIR_TX_MODE); if (a_kind == IR_SEND_CONTINUE) { IR_WRITE_CR11(IR_CR11_SEND_CONTINUE); } else { IR_WRITE_CR11(IR_CR_CLEAR); } IR_WRITE_CR26(IR_CR26_FIFO_RESET); IR_WRITE_CR27(IR_CR27_FIFO_TX_MODE); }
void ir_reg_CR0_reset(uint16 cr0_reset_val) { register uint16 w_dmy = IR_CR_CLEAR; uint16 cr0_set_val; uint16 check_val = (IR_CR0_TX_RESET | IR_CR0_RX_RESET | IR_CR0_TIMER_RESET | IR_CR0_SYSTEM_RESET | IR_CR0_CAREER_RESET); if ((cr0_reset_val & ~check_val) != 0x0000) { MSG_IRREG_ERR( "cr0_reset_val = 0x%x\n", (int)cr0_reset_val); } cr0_set_val = cr0_reset_val & check_val; IR_WRITE_CR0(cr0_set_val); *(volatile uint16*)IR_REG_CR14 = w_dmy; w_dmy = IR_READ_SR14; }
void ir_reg_irda_fir_set_tx(TYPE_IR_SEND_KIND a_kind) { IR_WRITE_CR15(IR_CR15_OPT_IO_A_CNN_ENA); IR_WRITE_CR0(IR_CR0_SEND_CNT_SEL); IR_WRITE_CR1(IR_CR1_DEFSET); IR_WRITE_CR2(IR_CR2_RX_OVERRUN_ERR_MSK | IR_CR2_RX_FLM_ERR_MSK | IR_CR2_RX_END_MSK | IR_CR2_TIMER_INTRPT_MSK | IR_CR2_RX_START_MSK); IR_WRITE_CR10(IR_CR10_FIR_TX_MODE); if (a_kind == IR_SEND_CONTINUE) { IR_WRITE_CR11(IR_CR11_SEND_CONTINUE); IR_WRITE_CR36(IR_CR36_FIR_INT_MODE); } else { IR_WRITE_CR11(IR_CR_CLEAR); IR_WRITE_CR36(IR_CR_CLEAR); } IR_WRITE_CR26(IR_CR26_FIFO_RESET); IR_WRITE_CR27(IR_CR27_FIFO_4M_TX_MODE); }
void ir_reg_irda_carrier_timer_int_clear(void) { IR_WRITE_CR0(IR_CR0_TIMER_RESET); }
void ir_reg_irda_fir_rx_restart(void) { IR_WRITE_CR0(IR_CR0_INT_RX_END | IR_CR0_INT_ENA); }
void ir_reg_irda_err_reset(void) { IR_WRITE_CR26(IR_CR26_FIFO_RESET); IR_WRITE_CR0(IR_CR0_TX_RESET | IR_CR0_RX_RESET | IR_CR0_CAREER_RESET); }