void ft_cpu_setup(void *blob, bd_t *bd) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; int spridr = immr->sysconf.spridr; /* * delete crypto node if not on an E-processor * initial revisions of the MPC834xE/6xE have the original SEC 2.0. * EA revisions got the SEC uprevved to 2.4 but since the default device * tree contains SEC 2.0 properties we uprev them here. */ if (!IS_E_PROCESSOR(spridr)) fdt_fixup_crypto_node(blob, 0); else if (IS_E_PROCESSOR(spridr) && (SPR_FAMILY(spridr) == SPR_834X_FAMILY || SPR_FAMILY(spridr) == SPR_836X_FAMILY) && REVID_MAJOR(spridr) >= 2) fdt_fixup_crypto_node(blob, 0x0204); #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) fdt_fixup_ethernet(blob); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", (bd->bi_busfreq / 4), 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", gd->core_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", "clock-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,immr", "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,immr", "clock-frequency", bd->bi_busfreq, 1); #ifdef CONFIG_QE ft_qe_setup(blob); #endif #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #if defined(CONFIG_BOOTCOUNT_LIMIT) fdt_fixup_muram (blob); #endif }
void set_liodns(void) { /* setup general liodn offsets */ set_liodn(liodn_tbl, liodn_tbl_sz); /* setup SEC block liodn bases & offsets if we have one */ if (IS_E_PROCESSOR(get_svr())) { set_liodn(sec_liodn_tbl, sec_liodn_tbl_sz); setup_sec_liodn_base(); } /* setup FMAN block(s) liodn bases & offsets if we have one */ #ifdef CONFIG_SYS_DPAA_FMAN set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, fman1_liodn_tbl_sz); #if (CONFIG_SYS_NUM_FMAN == 2) set_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, fman2_liodn_tbl_sz); #endif #endif /* setup PME liodn base */ setup_pme_liodn_base(); }
void ft_cpu_setup(void *blob, bd_t *bd) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); unsigned int svr = gur_in32(&gur->svr); /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(svr)) fdt_fixup_crypto_node(blob, 0); #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 else { ccsr_sec_t __iomem *sec; #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT if (fdt_fixup_kaslr(blob)) fdt_fixup_remove_jr(blob); #endif sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif #ifdef CONFIG_MP ft_fixup_cpu(blob); #endif #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif #ifdef CONFIG_FSL_ESDHC fdt_fixup_esdhc(blob, bd); #endif #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif #ifndef CONFIG_ARCH_LS1012A fsl_fdt_disable_usb(blob); #endif #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN fdt_fixup_gic(blob); #endif #ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI fdt_fixup_msi(blob); #endif }
static int fdt_cpu_setup(struct device_node *blob, void *unused) { struct device_node *node; struct sys_info sysinfo; /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(get_svr())) of_setup_crypto_node(blob); fdt_add_enet_stashing(blob); fsl_get_sys_info(&sysinfo); node = of_find_node_by_type(blob, "cpu"); while (node) { const uint32_t *reg; of_property_write_u32(node, "timebase-frequency", fsl_get_timebase_clock()); of_property_write_u32(node, "bus-frequency", sysinfo.freqSystemBus); reg = of_get_property(node, "reg", NULL); of_property_write_u32(node, "clock-frequency", sysinfo.freqProcessor[*reg]); node = of_find_node_by_type(node, "cpu"); } node = of_find_node_by_type(blob, "soc"); if (node) of_property_write_u32(node, "bus-frequency", sysinfo.freqSystemBus); node = of_find_compatible_node(blob, NULL, "fsl,elbc"); if (node) of_property_write_u32(node, "bus-frequency", sysinfo.freqLocalBus); node = of_find_compatible_node(blob, NULL, "ns16550"); while (node) { of_property_write_u32(node, "clock-frequency", sysinfo.freqSystemBus); node = of_find_compatible_node(node, NULL, "ns16550"); } node = of_find_compatible_node(blob, NULL, "fsl,mpic"); if (node) of_property_write_u32(node, "clock-frequency", sysinfo.freqSystemBus); fdt_stdout_setup(blob); return 0; }
static void setup_sec_liodn_base(void) { ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; u32 base; if (!IS_E_PROCESSOR(get_svr())) return; /* QILCR[QSLOM] */ out_be32(&sec->qilcr_ms, 0x3ff<<16); base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) | liodn_bases[FSL_HW_PORTAL_SEC].id[1]; out_be32(&sec->qilcr_ls, base); }
void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FSL_LSCH2 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); unsigned int svr = in_be32(&gur->svr); /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(svr)) fdt_fixup_crypto_node(blob, 0); #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 else { ccsr_sec_t __iomem *sec; sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif #endif #ifdef CONFIG_MP ft_fixup_cpu(blob); #endif #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif do_fixup_by_compat_u32(blob, "fixed-clock", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif #ifdef CONFIG_FSL_ESDHC fdt_fixup_esdhc(blob, bd); #endif #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif fsl_fdt_disable_usb(blob); }
void set_liodns(void) { /* setup general liodn offsets */ set_liodn(liodn_tbl, liodn_tbl_sz); #ifdef CONFIG_SYS_SRIO /* setup SRIO port liodns */ set_srio_liodn(srio_liodn_tbl, srio_liodn_tbl_sz); #endif /* setup SEC block liodn bases & offsets if we have one */ if (IS_E_PROCESSOR(get_svr())) { set_liodn(sec_liodn_tbl, sec_liodn_tbl_sz); setup_sec_liodn_base(); } /* setup FMAN block(s) liodn bases & offsets if we have one */ #ifdef CONFIG_SYS_DPAA_FMAN set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, fman1_liodn_tbl_sz); #if (CONFIG_SYS_NUM_FMAN == 2) set_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, fman2_liodn_tbl_sz); #endif #endif /* setup PME liodn base */ setup_pme_liodn_base(); #ifdef CONFIG_SYS_FSL_RAID_ENGINE /* raid engine ccr addr code for liodn */ set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz); setup_raide_liodn_base(); #endif #ifdef CONFIG_SYS_DPAA_RMAN /* setup RMan liodn offsets */ set_rman_liodn(rman_liodn_tbl, rman_liodn_tbl_sz); /* setup RMan liodn base */ setup_rman_liodn_base(rman_liodn_tbl, rman_liodn_tbl_sz); #endif }
void ft_cpu_setup(void *blob, bd_t *bd) { int off; int val; const char *sysclk_path; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); unsigned int svr; svr = in_be32(&gur->svr); unsigned long busclk = get_bus_freq(0); /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(svr)) fdt_fixup_crypto_node(blob, 0); #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 else { ccsr_sec_t __iomem *sec; sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { val = gd->cpu_clk; fdt_setprop(blob, off, "clock-frequency", &val, 4); off = fdt_node_offset_by_prop_value(blob, off, "device_type", "cpu", 4); } do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", busclk, 1); ft_fixup_enet_phy_connect_type(blob); #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif sysclk_path = fdt_get_alias(blob, "sysclk"); if (sysclk_path) do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT) #define UBOOT_HEAD_LEN 0x1000 /* * Reserved memory in SD boot deep sleep case. * Second stage uboot binary and malloc space should be reserved. * If the memory they occupied has not been reserved, then this * space would be used by kernel and overwritten in uboot when * deep sleep resume, which cause deep sleep failed. * Since second uboot binary has a head, that space need to be * reserved either(assuming its size is less than 0x1000). */ off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN, CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE + UBOOT_HEAD_LEN); if (off < 0) printf("Failed to reserve memory for SD boot deep sleep: %s\n", fdt_strerror(off)); #endif #if defined(CONFIG_FSL_ESDHC) fdt_fixup_esdhc(blob, bd); #endif /* * platform bus clock = system bus clock/2 * Here busclk = system bus clock * We are using the platform bus clock as 1588 Timer reference * clock source select */ do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer", "timer-frequency", busclk / 2, 1); /* * clock-freq should change to clock-frequency and * flexcan-v1.0 should change to p1010-flexcan respectively * in the future. */ do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", "clock_freq", busclk / 2, 1); do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", "clock-frequency", busclk / 2, 1); do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", "clock-frequency", busclk / 2, 1); #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, CONFIG_SYS_IFC_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); #else off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, QSPI0_BASE_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT, DSPI1_BASE_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); #endif }
void ft_cpu_setup(void *blob, bd_t *bd) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; int spridr = immr->sysconf.spridr; /* * delete crypto node if not on an E-processor * initial revisions of the MPC834xE/6xE have the original SEC 2.0. * EA revisions got the SEC uprevved to 2.4 but since the default device * tree contains SEC 2.0 properties we uprev them here. */ if (!IS_E_PROCESSOR(spridr)) fdt_fixup_crypto_node(blob, 0); else if (IS_E_PROCESSOR(spridr) && (SPR_FAMILY(spridr) == SPR_834X_FAMILY || SPR_FAMILY(spridr) == SPR_836X_FAMILY) && REVID_MAJOR(spridr) >= 2) fdt_fixup_crypto_node(blob, 0x0204); #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) fdt_fixup_ethernet(blob); #ifdef CONFIG_MPC8313 /* * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 * h/w (see AN3545). The base device tree in use has rev. 1 ID numbers, * so if on Rev. 2 (and higher) h/w, we fix them up here */ if (REVID_MAJOR(immr->sysconf.spridr) >= 2) { int nodeoffset, path; const char *prop; nodeoffset = fdt_path_offset(blob, "/aliases"); if (nodeoffset >= 0) { #if defined(CONFIG_HAS_ETH0) prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL); if (prop) { u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 }; path = fdt_path_offset(blob, prop); prop = fdt_getprop(blob, path, "interrupts", NULL); if (prop) fdt_setprop(blob, path, "interrupts", &tmp, sizeof(tmp)); } #endif #if defined(CONFIG_HAS_ETH1) prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL); if (prop) { u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 }; path = fdt_path_offset(blob, prop); prop = fdt_getprop(blob, path, "interrupts", NULL); if (prop) fdt_setprop(blob, path, "interrupts", &tmp, sizeof(tmp)); } #endif } } #endif #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", (bd->bi_busfreq / 4), 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", gd->arch.core_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", "clock-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,immr", "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,immr", "clock-frequency", bd->bi_busfreq, 1); #ifdef CONFIG_QE ft_qe_setup(blob); #endif #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) fdt_fixup_muram (blob); #endif }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint fam; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else #ifdef CONFIG_FSL_CORENET u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_FSL_CORENET */ #endif /* CONFIG_DDR_CLK_FREQ */ int i; svr = get_svr(); major = SVR_MAJ(svr); #ifdef CONFIG_MPC8536 major &= 0x7; /* the msb of this nibble is a mfg code */ #endif minor = SVR_MIN(svr); if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); if (PVR_FAM(PVR_85xx)) { switch(PVR_MEM(pvr)) { case 0x1: case 0x2: puts("E500"); break; case 0x3: puts("E500MC"); break; case 0x4: puts("E5500"); break; default: puts("Unknown"); break; } } else { puts("Unknown"); } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:"); for (i = 0; i < cpu_numcores(); i++) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", i,strmhz(buf1, sysinfo.freqProcessor[i])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freqFMan[i])); } #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ uint pvr, svr; uint fam; uint ver; uint major, minor; struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; #else u32 ddr_ratio = 0; #endif svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); #ifdef CONFIG_MPC8536 major &= 0x7; /* the msb of this nibble is a mfg code */ #endif minor = SVR_MIN(svr); puts("CPU: "); cpu = identify_cpu(ver); if (cpu) { puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); } else { puts("Unknown"); } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch (fam) { case PVR_FAM(PVR_85xx): puts("E500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:\n"); printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); switch (ddr_ratio) { case 0x0: printf(" DDR:%4lu MHz (%lu MT/s data rate), ", DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); break; case 0x7: printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000)); break; default: printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); break; } #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else { volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. */ clkdiv *= 2; #endif printf("LBC:%4lu MHz\n", DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv); } else { printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); } #ifdef CONFIG_CPM2 printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint fam; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif int i; svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); #ifdef CONFIG_MPC8536 major &= 0x7; /* the msb of this nibble is a mfg code */ #endif minor = SVR_MIN(svr); #if (CONFIG_NUM_CPUS > 1) volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); printf("CPU%d: ", pic->whoami); #else puts("CPU: "); #endif cpu = identify_cpu(ver); if (cpu) { puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); } else { puts("Unknown"); } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch (fam) { case PVR_FAM(PVR_85xx): puts("E500"); break; default: puts("Unknown"); break; } if (PVR_MEM(pvr) == 0x03) puts("MC"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:"); for (i = 0; i < CONFIG_NUM_CPUS; i++) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", i,strmhz(buf1, sysinfo.freqProcessor[i])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } if (sysinfo.freqLocalBus > LCRR_CLKDIV) printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); else printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async * mode. Previous platform use ddr ratio to do the same. This * information is only for display here. */ #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 u32 ddr_sync = 0; /* only async mode is supported */ #else u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_DDR_CLK_FREQ */ #endif /* CONFIG_FSL_CORENET */ unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->arch.cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch(ver) { case PVR_VER_E500_V1: case PVR_VER_E500_V2: puts("e500"); break; case PVR_VER_E500MC: puts("e500mc"); break; case PVR_VER_E5500: puts("e5500"); break; case PVR_VER_E6500: puts("e6500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); if (nr_cores > CONFIG_MAX_CPUS) { panic("\nUnexpected number of cores: %d, max is %d\n", nr_cores, CONFIG_MAX_CPUS); } get_sys_info(&sysinfo); puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freqProcessor[core])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } #endif #if defined(CONFIG_FSL_IFC) printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freqFMan[i])); } #endif #ifdef CONFIG_SYS_DPAA_QBMAN printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN)); #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); #ifdef CONFIG_FSL_CORENET /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { u32 rcw = in_be32(&gur->rcwsr[i]); if ((i % 4) == 0) printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); #endif return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async * mode. Previous platform use ddr ratio to do the same. This * information is only for display here. */ #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 u32 ddr_sync = 0; /* only async mode is supported */ #else u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_DDR_CLK_FREQ */ #endif /* CONFIG_FSL_CORENET */ unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); #ifdef CONFIG_HETROGENOUS_CLUSTERS unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores(); u32 dsp_mask = cpu_dsp_mask(); #endif svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) if (SVR_SOC_VER(svr) == SVR_T4080) { ccsr_rcpm_t *rcpm = (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || FSL_CORENET_DEVDISR2_DTSEC1_9); setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); /* It needs SW to disable core4~7 as HW design sake on T4080 */ for (i = 4; i < 8; i++) cpu_disable(i); /* request core4~7 into PH20 state, prior to entering PCL10 * state, all cores in cluster should be placed in PH20 state. */ setbits_be32(&rcpm->pcph20setr, 0xf0); /* put the 2nd cluster into PCL10 state */ setbits_be32(&rcpm->clpcl10setr, 1 << 1); } #endif if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->arch.cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch(ver) { case PVR_VER_E500_V1: case PVR_VER_E500_V2: puts("e500"); break; case PVR_VER_E500MC: puts("e500mc"); break; case PVR_VER_E5500: puts("e5500"); break; case PVR_VER_E6500: puts("e6500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); if (nr_cores > CONFIG_MAX_CPUS) { panic("\nUnexpected number of cores: %d, max is %d\n", nr_cores, CONFIG_MAX_CPUS); } get_sys_info(&sysinfo); #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK if (sysinfo.diff_sysclk == 1) puts("Single Source Clock Configuration\n"); #endif puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freq_processor[core])); } #ifdef CONFIG_HETROGENOUS_CLUSTERS for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) { if (!(j & 3)) printf("\n "); printf("DSP CPU%d:%-4s MHz, ", j, strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core])); } #endif printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); printf("\n"); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freq_localbus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freq_localbus); } #endif #if defined(CONFIG_FSL_IFC) printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); #endif #if defined(CONFIG_SYS_CPRI) printf(" "); printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri)); #endif #if defined(CONFIG_SYS_MAPLE) printf("\n "); printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple)); printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb)); printf("MAPLE-eTVPE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_maple_etvpe)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freq_fman[i])); } #endif #ifdef CONFIG_SYS_DPAA_QBMAN printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman)); #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); #endif puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); #ifdef CONFIG_FSL_CORENET /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { u32 rcw = in_be32(&gur->rcwsr[i]); if ((i % 4) == 0) printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); #endif return 0; }