static void pwm_process(uint16_t *buffer)
{
while (pwm_read_pos != pwm_write_pos)
{
static uint8_t pins = 0;
uint16_t time = pwm_buffer[pwm_read_pos].time;
uint8_t current = pwm_buffer[pwm_read_pos].pins;
uint8_t changed = pins ^ current;
pins = current;
uint8_t pin = _BV(7);
for (int i=0; i<CHANNELS; i++)
{
if (changed & pin)
{
if (IS_RISING_EDGE(current & pin))
{
/* Rising edge, store time */
pwm_rise_times[i] = time;
}
else
{
/* Falling edge, calculate pulse length */
uint16_t pulse_width = time - pwm_rise_times[i];
if (pulse_width < PWM_PULSE_MIN_WIDTH)
pulse_width = PWM_PULSE_MIN_WIDTH;
else if (pulse_width > PWM_PULSE_MAX_WIDTH)
pulse_width = PWM_PULSE_MAX_WIDTH;
buffer[i] = pulse_width;
}
}
pin >>= 1;
}
/* This is not atomic, so protect it with cli/sei */
cli();
pwm_read_pos = (pwm_read_pos + 1) & PWM_BUFFER_MASK;
sei();
}
}
static int stm32_sdmmc2_set_ios(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
struct mmc_config *cfg = &plat->cfg;
u32 desired = mmc->clock;
u32 sys_clock = clk_get_rate(&priv->clk);
u32 clk = 0;
debug("%s: bus_with = %d, clock = %d\n", __func__,
mmc->bus_width, mmc->clock);
if ((mmc->bus_width == 1) && (desired == cfg->f_min))
stm32_sdmmc2_pwron(priv);
/*
* clk_div = 0 => command and data generated on SDMMCCLK falling edge
* clk_div > 0 and NEGEDGE = 0 => command and data generated on
* SDMMCCLK rising edge
* clk_div > 0 and NEGEDGE = 1 => command and data generated on
* SDMMCCLK falling edge
*/
if (desired && ((sys_clock > desired) ||
IS_RISING_EDGE(priv->clk_reg_msk))) {
clk = DIV_ROUND_UP(sys_clock, 2 * desired);
if (clk > SDMMC_CLKCR_CLKDIV_MAX)
clk = SDMMC_CLKCR_CLKDIV_MAX;
}
if (mmc->bus_width == 4)
clk |= SDMMC_CLKCR_WIDBUS_4;
if (mmc->bus_width == 8)
clk |= SDMMC_CLKCR_WIDBUS_8;
writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
priv->base + SDMMC_CLKCR);
return 0;
}
