/*
Description : Send PSMP Action frame If PSMP mode switches.
*/
VOID SendPSMPAction(
IN PRTMP_ADAPTER pAd,
IN UCHAR Wcid,
IN UCHAR Psmp)
{
PUCHAR pOutBuffer = NULL;
NDIS_STATUS NStatus;
//ULONG Idx;
FRAME_PSMP_ACTION Frame;
ULONG FrameLen;
NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); //Get an unused nonpaged memory
if (NStatus != NDIS_STATUS_SUCCESS)
{
DBGPRINT(RT_DEBUG_ERROR,("BA - MlmeADDBAAction() allocate memory failed \n"));
return;
}
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
ActHeaderInit(pAd, &Frame.Hdr, pAd->CommonCfg.Bssid, pAd->CurrentAddress, pAd->MacTab.Content[Wcid].Addr);
#endif // CONFIG_STA_SUPPORT //
Frame.Category = CATEGORY_HT;
Frame.Action = SMPS_ACTION;
switch (Psmp)
{
case MMPS_ENABLE:
#ifdef RT30xx
if (IS_RT30xx(pAd)
&&(pAd->Antenna.field.RxPath>1||pAd->Antenna.field.TxPath>1))
{
RTMP_ASIC_MMPS_DISABLE(pAd);
}
#endif // RT30xx //
Frame.Psmp = 0;
break;
case MMPS_DYNAMIC:
Frame.Psmp = 3;
break;
case MMPS_STATIC:
#ifdef RT30xx
if (IS_RT30xx(pAd)
&&(pAd->Antenna.field.RxPath>1||pAd->Antenna.field.TxPath>1))
{
RTMP_ASIC_MMPS_ENABLE(pAd);
}
#endif // RT30xx //
Frame.Psmp = 1;
break;
}
MakeOutgoingFrame(pOutBuffer, &FrameLen,
sizeof(FRAME_PSMP_ACTION), &Frame,
END_OF_ARGS);
MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
MlmeFreeMemory(pAd, pOutBuffer);
DBGPRINT(RT_DEBUG_ERROR,("HT - SendPSMPAction( %d ) \n", Frame.Psmp));
}
/*
Description : Send PSMP Action frame If PSMP mode switches.
*/
void SendPSMPAction(struct rt_rtmp_adapter *pAd, u8 Wcid, u8 Psmp)
{
u8 *pOutBuffer = NULL;
int NStatus;
/*unsigned long Idx; */
struct rt_frame_psmp_action Frame;
unsigned long FrameLen;
NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
if (NStatus != NDIS_STATUS_SUCCESS) {
DBGPRINT(RT_DEBUG_ERROR,
("BA - MlmeADDBAAction() allocate memory failed \n"));
return;
}
ActHeaderInit(pAd, &Frame.Hdr, pAd->CommonCfg.Bssid,
pAd->CurrentAddress, pAd->MacTab.Content[Wcid].Addr);
Frame.Category = CATEGORY_HT;
Frame.Action = SMPS_ACTION;
switch (Psmp) {
case MMPS_ENABLE:
#ifdef RT30xx
if (IS_RT30xx(pAd)
&& (pAd->Antenna.field.RxPath > 1
|| pAd->Antenna.field.TxPath > 1)) {
RTMP_ASIC_MMPS_DISABLE(pAd);
}
#endif /* RT30xx // */
Frame.Psmp = 0;
break;
case MMPS_DYNAMIC:
Frame.Psmp = 3;
break;
case MMPS_STATIC:
#ifdef RT30xx
if (IS_RT30xx(pAd)
&& (pAd->Antenna.field.RxPath > 1
|| pAd->Antenna.field.TxPath > 1)) {
RTMP_ASIC_MMPS_ENABLE(pAd);
}
#endif /* RT30xx // */
Frame.Psmp = 1;
break;
}
MakeOutgoingFrame(pOutBuffer, &FrameLen,
sizeof(struct rt_frame_psmp_action), &Frame, END_OF_ARGS);
MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
MlmeFreeMemory(pAd, pOutBuffer);
DBGPRINT(RT_DEBUG_ERROR, ("HT - SendPSMPAction( %d ) \n", Frame.Psmp));
}
static INT rtmp_bbp_init(RTMP_ADAPTER *pAd)
{
INT Index = 0;
/* Read BBP register, make sure BBP is up and running before write new data*/
if (rtmp_bbp_is_ready(pAd)== FALSE)
return FALSE;
Index = 0;
/* Initialize BBP register to default value*/
for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++)
{
#ifdef MICROWAVE_OVEN_SUPPORT
#endif /* MICROWAVE_OVEN_SUPPORT */
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd,
BBPRegTable[Index].Register,
BBPRegTable[Index].Value);
}
/* re-config specific BBP registers for individual chip */
if (pAd->chipCap.pBBPRegTable)
{
REG_PAIR *reg_list = pAd->chipCap.pBBPRegTable;
for (Index = 0; Index < pAd->chipCap.bbpRegTbSize; Index++)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd,
reg_list[Index].Register,
reg_list[Index].Value);
DBGPRINT(RT_DEBUG_TRACE, ("BBP_R%d=0x%x\n",
reg_list[Index].Register,
reg_list[Index].Value));
}
}
if (pAd->chipOps.AsicBbpInit != NULL)
pAd->chipOps.AsicBbpInit(pAd);
/*
For rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT.
RT3090 should not program BBP R84 to 0x19, otherwise TX will block.
3070/71/72,3090,3090A( are included in RT30xx),3572,3390
*/
if (((pAd->MACVersion & 0xffff) != 0x0101) &&
!(IS_RT30xx(pAd)|| IS_RT3572(pAd) || IS_RT5390(pAd) || IS_RT5392(pAd) || IS_RT3290(pAd) || IS_MT7601(pAd) || IS_RT6352(pAd) || IS_MT76x2(pAd)))
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19);
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12);
}
return TRUE;
}
VOID RtmpChipOpsRFHook(
IN RTMP_ADAPTER *pAd)
{
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
pChipOps->pRFRegTable = NULL;
pChipOps->pBBPRegTable = NULL;
pChipOps->AsicRfInit = NULL;
pChipOps->AsicRfTurnOn = NULL;
pChipOps->AsicRfTurnOff = NULL;
pChipOps->AsicReverseRfFromSleepMode = NULL;
pChipOps->AsicHaltAction = NULL;
/* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
#ifdef RT30xx
#ifdef RT3593
if (IS_RT3593(pAd))
{
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->pRFRegTable = RF3053RegTable;
pChipOps->AsicRfInit = NICInitRT3593RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup;
pChipOps->AsicHaltAction = RT30xxHaltAction;
}
#endif // RT3593 //
if (IS_RT30xx(pAd))
{
/*
WARNING:
Currently following table are shared by all RT30xx based IC, change it carefully when you add a new IC here.
*/
pChipOps->pRFRegTable = RT3020_RFRegTable;
pChipOps->AsicHaltAction = RT30xxHaltAction;
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup;
#ifdef RT3070
if((IS_RT3070(pAd) || IS_RT3071(pAd)) && (pAd->infType == RTMP_DEV_INF_USB))
{
pChipOps->AsicRfInit = NICInitRT3070RFRegisters;
}
#endif // RT3070 //
}
#endif // RT30xx //
if (pChipOps->pBBPRegTable != NULL)
pChipOps->bbpRegTbSize = (sizeof(*(pChipOps->pBBPRegTable)) / sizeof(REG_PAIR));
DBGPRINT(RT_DEBUG_TRACE, ("Chip specific bbpRegTbSize=%d!\n", pChipOps->bbpRegTbSize));
}
VOID RtmpChipOpsRFHook(
IN RTMP_ADAPTER *pAd)
{
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
pChipOps->pRFRegTable = NULL;
pChipOps->pBBPRegTable = NULL;
pChipOps->bbpRegTbSize = 0;
pChipOps->AsicRfInit = NULL;
pChipOps->AsicRfTurnOn = NULL;
pChipOps->AsicRfTurnOff = NULL;
pChipOps->AsicReverseRfFromSleepMode = NULL;
pChipOps->AsicHaltAction = NULL;
/* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
#ifdef RT30xx
#ifdef RT35xx
if (IS_RT3572(pAd))
{
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->pRFRegTable = RF3572_RFRegTable;
pChipOps->AsicRfInit = NICInitRT3572RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT3572ReverseRFSleepModeSetup;
pChipOps->AsicHaltAction = RT30xxHaltAction;
}
#endif // RT35xx //
if (IS_RT30xx(pAd))
{
/*
WARNING:
Currently following table are shared by all RT30xx based IC, change it carefully when you add a new IC here.
*/
pChipOps->pRFRegTable = RT3020_RFRegTable;
pChipOps->AsicHaltAction = RT30xxHaltAction;
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup;
}
#endif // RT30xx //
DBGPRINT(RT_DEBUG_TRACE, ("Chip specific bbpRegTbSize=%d!\n", pChipOps->bbpRegTbSize));
}
VOID RtmpChipOpsRFHook(
IN RTMP_ADAPTER *pAd)
{
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
pChipOps->pRFRegTable = NULL;
pChipOps->AsicRfInit = NULL;
pChipOps->AsicRfTurnOn = NULL;
pChipOps->AsicRfTurnOff = NULL;
pChipOps->AsicReverseRfFromSleepMode = NULL;
pChipOps->AsicHaltAction = NULL;
#ifdef RT33xx
if (IS_RT3390(pAd) && (pAd->infType == RTMP_DEV_INF_PCI))
{
pChipOps->pRFRegTable = RFRegTableOverRT3390;
pChipOps->AsicHaltAction = RT33xxHaltAction;
pChipOps->AsicRfTurnOff = RT33xxLoadRFSleepModeSetup;
pChipOps->AsicRfInit = NICInitRT3390RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT33xxReverseRFSleepModeSetup;
}
#else
#ifdef RT30xx
if (IS_RT30xx(pAd))
{
pChipOps->pRFRegTable = RT30xx_RFRegTable;
pChipOps->AsicHaltAction = RT30xxHaltAction;
#ifdef RT3090
if (IS_RT3090(pAd) && (pAd->infType == RTMP_DEV_INF_PCI))
{
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->AsicRfInit = NICInitRT3090RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup;
}
#endif
}
#endif
#endif
}
VOID RtmpChipOpsRFHook(
IN RTMP_ADAPTER *pAd)
{
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
pChipOps->pRFRegTable = NULL;
pChipOps->AsicRfInit = NULL;
pChipOps->AsicRfTurnOn = NULL;
pChipOps->AsicRfTurnOff = NULL;
pChipOps->AsicReverseRfFromSleepMode = NULL;
pChipOps->AsicHaltAction = NULL;
#ifdef RT33xx
if (IS_RT3390(pAd) && (pAd->infType == RTMP_DEV_INF_PCI))
{
pChipOps->pRFRegTable = RFRegTableOverRT3390;
pChipOps->AsicHaltAction = RT33xxHaltAction;
pChipOps->AsicRfTurnOff = RT33xxLoadRFSleepModeSetup;
pChipOps->AsicRfInit = NICInitRT3390RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT33xxReverseRFSleepModeSetup;
}
#else // RT33xx //
/* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
#ifdef RT30xx
if (IS_RT30xx(pAd))
{
pChipOps->pRFRegTable = RT30xx_RFRegTable;
pChipOps->AsicHaltAction = RT30xxHaltAction;
#ifdef RT3090
if (IS_RT3090(pAd) && (pAd->infType == RTMP_DEV_INF_PCI))
{
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->AsicRfInit = NICInitRT3090RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup;
}
#endif // RT3090 //
}
#endif // RT30xx //
#endif // RT33xx //
}
void RtmpChipOpsRFHook(struct rt_rtmp_adapter *pAd)
{
struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps;
pChipOps->pRFRegTable = NULL;
pChipOps->AsicRfInit = NULL;
pChipOps->AsicRfTurnOn = NULL;
pChipOps->AsicRfTurnOff = NULL;
pChipOps->AsicReverseRfFromSleepMode = NULL;
pChipOps->AsicHaltAction = NULL;
/* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
#ifdef RT30xx
if (IS_RT30xx(pAd)) {
pChipOps->pRFRegTable = RT30xx_RFRegTable;
pChipOps->AsicHaltAction = RT30xxHaltAction;
#ifdef RT3070
if ((IS_RT3070(pAd) || IS_RT3071(pAd))
&& (pAd->infType == RTMP_DEV_INF_USB)) {
pChipOps->AsicRfInit = NICInitRT3070RFRegisters;
if (IS_RT3071(pAd)) {
pChipOps->AsicRfTurnOff =
RT30xxLoadRFSleepModeSetup;
pChipOps->AsicReverseRfFromSleepMode =
RT30xxReverseRFSleepModeSetup;
}
}
#endif /* RT3070 // */
#ifdef RT3090
if (IS_RT3090(pAd) && (pAd->infType == RTMP_DEV_INF_PCI)) {
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->AsicRfInit = NICInitRT3090RFRegisters;
pChipOps->AsicReverseRfFromSleepMode =
RT30xxReverseRFSleepModeSetup;
}
#endif /* RT3090 // */
}
#endif /* RT30xx // */
}
VOID RT30xx_ChipSwitchChannel(
IN PRTMP_ADAPTER pAd,
IN UCHAR Channel,
IN BOOLEAN bScan)
{
CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/
UCHAR index;
UINT32 Value = 0; /*BbpReg, Value;*/
UCHAR RFValue;
UINT32 i = 0;
UCHAR Tx0FinePowerCtrl = 0, Tx1FinePowerCtrl = 0;
BBP_R109_STRUC BbpR109 = {{0}};
i = i; /* avoid compile warning */
RFValue = 0;
/* Search Tx power value*/
/*
We can't use ChannelList to search channel, since some central channl's txpowr doesn't list
in ChannelList, so use TxPower array instead.
*/
for (index = 0; index < MAX_NUM_OF_CHANNELS; index++)
{
if (Channel == pAd->TxPower[index].Channel)
{
TxPwer = pAd->TxPower[index].Power;
TxPwer2 = pAd->TxPower[index].Power2;
#ifdef RT33xx
#endif /* RT33xx */
break;
}
}
if (index == MAX_NUM_OF_CHANNELS)
{
DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel));
}
#ifdef RT30xx
/* The RF programming sequence is difference between 3xxx and 2xxx*/
if ((IS_RT30xx(pAd)) &&
((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) ||
(pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) || (pAd->RfIcType == RFIC_3320)))
{
/* modify by WY for Read RF Reg. error */
UCHAR calRFValue;
for (index = 0; index < NUM_OF_3020_CHNL; index++)
{
if (Channel == FreqItems3020[index].Channel)
{
/* Programming channel parameters*/
RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3020[index].N);
/*
RT3370/RT3390 RF version is 0x3320 RF_R3 [7:4] is not reserved bits
RF_R3[6:4] (pa1_bc_cck) : PA1 Bias CCK
RF_R3[7] (pa2_cc_cck) : PA2 Cascode Bias CCK
*/
RT30xxReadRFRegister(pAd, RF_R03, (PUCHAR)(&RFValue));
RFValue = (RFValue & 0xF0) | (FreqItems3020[index].K & ~0xF0); /* <bit 3:0>:K<bit 3:0>*/
RT30xxWriteRFRegister(pAd, RF_R03, RFValue);
RT30xxReadRFRegister(pAd, RF_R06, &RFValue);
RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
RT30xxWriteRFRegister(pAd, RF_R06, RFValue);
/* Set Tx0 Power*/
RT30xxReadRFRegister(pAd, RF_R12, &RFValue);
RFValue = (RFValue & 0xE0) | TxPwer;
RT30xxWriteRFRegister(pAd, RF_R12, RFValue);
/*Set Tx1 Power*/
RT30xxReadRFRegister(pAd, RF_R13, &RFValue);
RFValue = (RFValue & 0xE0) | TxPwer2;
RT30xxWriteRFRegister(pAd, RF_R13, RFValue);
#ifdef RT33xx
#endif /* RT33xx */
/* Tx/Rx Stream setting*/
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= 0x03; /*clear bit[7~2]*/
if (pAd->Antenna.field.TxPath == 1)
RFValue |= 0xA0;
else if (pAd->Antenna.field.TxPath == 2)
RFValue |= 0x80;
if (pAd->Antenna.field.RxPath == 1)
RFValue |= 0x50;
else if (pAd->Antenna.field.RxPath == 2)
RFValue |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
/* Set RF offset*/
RT30xxReadRFRegister(pAd, RF_R23, &RFValue);
RFValue = (RFValue & 0x80) | pAd->RfFreqOffset;
RT30xxWriteRFRegister(pAd, RF_R23, RFValue);
/* Set BW*/
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
{
calRFValue = pAd->Mlme.CaliBW40RfR24;
}
else
{
calRFValue = pAd->Mlme.CaliBW20RfR24;
}
/*
RT3370/RT3390 RF version is 0x3320 RF_R24 [7:6] is not reserved bits
RF_R24[6] (BB_Rx1_out_en) : enable baseband output and ADC input
RF_R24[7] (BB_Tx1_out_en) : enable DAC output or baseband input
*/
RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RFValue));
calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0>*/
RT30xxWriteRFRegister(pAd, RF_R24, calRFValue);
/*
RT3370/RT3390 RF version is 0x3320 RF_R31 [7:6] is not reserved bits
RF_R31[4:0] (rx_agc_fc) : capacitor control in baseband filter
RF_R31[5] (rx_ h20M) : rx_ h20M: 0=10 MHz and 1=20MHz
RF_R31[7:6] (drv_bc_cck) : Driver Bias CCK
*/
/* Set BW*/
if (IS_RT3390(pAd)) /* RT3390 has different AGC for Tx and Rx*/
{
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
{
calRFValue = pAd->Mlme.CaliBW40RfR31;
}
else
{
calRFValue = pAd->Mlme.CaliBW20RfR31;
}
}
RT30xxReadRFRegister(pAd, RF_R31, (PUCHAR)(&RFValue));
calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:rx_h20M<bit 5> and <bit 4:0>:rx_agc_fc<bit 4:0>*/
RT30xxWriteRFRegister(pAd, RF_R31, calRFValue);
/* Enable RF tuning*/
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue = RFValue | 0x1;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
/* latch channel for future usage.*/
pAd->LatchRfRegs.Channel = Channel;
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
Channel,
pAd->RfIcType,
TxPwer,
TxPwer2,
pAd->Antenna.field.TxPath,
FreqItems3020[index].N,
FreqItems3020[index].K,
FreqItems3020[index].R));
break;
}
}
}
else
#endif /* RT30xx */
{
switch (pAd->RfIcType)
{
default:
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n",
Channel, pAd->RfIcType));
break;
}
}
/* Change BBP setting during siwtch from a->g, g->a*/
if (Channel <= 14)
{
ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/
/* Rx High power VGA offset for LNA select*/
{
if (pAd->NicConfig2.field.ExternalLNAForG)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x04);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
else
{
ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/
UINT8 bbpValue;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/
/* Set the BBP_R82 value here */
bbpValue = 0xF2;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue);
/* Rx High power VGA offset for LNA select*/
if (pAd->NicConfig2.field.ExternalLNAForA)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R*/
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
/* R66 should be set according to Channel and use 20MHz when scanning*/
if (bScan)
RTMPSetAGCInitValue(pAd, BW_20);
else
RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW);
/*
On 11A, We should delay and wait RF/BBP to be stable
and the appropriate time should be 1000 micro seconds
2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.
*/
RTMPusecDelay(1000);
}
NDIS_STATUS NICInitBBP(RTMP_ADAPTER *pAd)
{
INT Index = 0;
/* Read BBP register, make sure BBP is up and running before write new data*/
if (rtmp_bbp_is_ready(pAd)== FALSE)
return NDIS_STATUS_FAILURE;
Index = 0;
/* Initialize BBP register to default value*/
for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++)
{
#ifdef MICROWAVE_OVEN_SUPPORT
#ifdef MT7601
if ( BBPRegTable[Index].Register == BBP_R65)
{
/* Backup BBP_R65 and B5.R6 and B5.R7 */
pAd->CommonCfg.MO_Cfg.Stored_BBP_R65 = BBPRegTable[Index].Value;
DBGPRINT(RT_DEBUG_TRACE, ("Stored_BBP_R65=%x @%s \n", pAd->CommonCfg.MO_Cfg.Stored_BBP_R65, __FUNCTION__));
}
#endif /* MT7601 */
#endif /* MICROWAVE_OVEN_SUPPORT */
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd,
BBPRegTable[Index].Register,
BBPRegTable[Index].Value);
}
/* re-config specific BBP registers for individual chip */
if (pAd->chipCap.pBBPRegTable)
{
REG_PAIR *pbbpRegTb = pAd->chipCap.pBBPRegTable;
for (Index = 0; Index < pAd->chipCap.bbpRegTbSize; Index++)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd,
pbbpRegTb[Index].Register,
pbbpRegTb[Index].Value);
DBGPRINT(RT_DEBUG_TRACE, ("BBP_R%d=0x%x\n",
pbbpRegTb[Index].Register,
pbbpRegTb[Index].Value));
}
}
if (pAd->chipOps.AsicBbpInit != NULL)
pAd->chipOps.AsicBbpInit(pAd);
/*
For rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT.
RT3090 should not program BBP R84 to 0x19, otherwise TX will block.
3070/71/72,3090,3090A( are included in RT30xx),3572,3390
*/
if (((pAd->MACVersion & 0xffff) != 0x0101) &&
!(IS_RT30xx(pAd)|| IS_RT3572(pAd) || IS_RT5390(pAd) || IS_RT5392(pAd) || IS_RT3290(pAd) || IS_MT7601(pAd)))
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19);
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12);
}
return NDIS_STATUS_SUCCESS;
}
VOID RT30xxATEAsicSwitchChannel(
IN PRTMP_ADAPTER pAd)
{
CHAR TxPwer = 0, TxPwer2 = 0;
UCHAR index = 0, Channel = 0;
UINT32 Value = 0;
#ifdef A_BAND_SUPPORT
UCHAR BbpValue = 0;
#endif /* A_BAND_SUPPORT */
#ifdef RTMP_RF_RW_SUPPORT
/* Added to prevent RF register reading error */
UCHAR RFValue = 0;
#endif /* RTMP_RF_RW_SUPPORT */
#ifdef RALINK_QA
/* For QA mode, TX power values are passed from UI */
if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
{
if (pAd->ate.Channel != pAd->LatchRfRegs.Channel)
{
pAd->ate.Channel = pAd->LatchRfRegs.Channel;
}
return;
}
else
#endif /* RALINK_QA */
Channel = pAd->ate.Channel;
/* Fill Tx power value */
TxPwer = pAd->ate.TxPower0;
TxPwer2 = pAd->ate.TxPower1;
/*
The RF programming sequence is difference between 3xxx and 2xxx.
The 3070 is 1T1R. Therefore, we don't need to set the number of Tx/Rx path
and the only job is to set the parameters of channels.
*/
if ((IS_RT30xx(pAd)) &&
((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) ||
(pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) || (pAd->RfIcType == RFIC_3320)))
{
for (index = 0; index < NUM_OF_3020_CHNL; index++)
{
if (Channel == FreqItems3020[index].Channel)
{
/* Programming channel parameters. */
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R02, FreqItems3020[index].N);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R03, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xF0) | (FreqItems3020[index].K&(~0xF0));
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R03, (UCHAR)RFValue);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R06, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R06, (UCHAR)RFValue);
/* Set Tx Power. */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R12, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xE0) | TxPwer;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R12, (UCHAR)RFValue);
/* Set RF offset. */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R23, (PUCHAR)&RFValue);
RFValue = (RFValue & 0x80) | pAd->ate.RFFreqOffset;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R23, (UCHAR)RFValue);
/* Set BW. */
if (pAd->ate.TxWI.BW == BW_40)
{
RFValue = pAd->Mlme.CaliBW40RfR24;
}
else
{
RFValue = pAd->Mlme.CaliBW20RfR24;
}
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R24, (UCHAR)RFValue);
/* Enable RF tuning */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R07, (PUCHAR)&RFValue);
RFValue = RFValue | 0x1;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R07, (UCHAR)RFValue);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
/* Latch channel for future usage */
pAd->LatchRfRegs.Channel = Channel;
ATEAsicSetTxRxPath(pAd);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
break;
}
}
DBGPRINT(RT_DEBUG_TRACE, ("%s::SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
__FUNCTION__,
Channel,
pAd->RfIcType,
TxPwer,
TxPwer2,
pAd->Antenna.field.TxPath,
FreqItems3020[index].N,
FreqItems3020[index].K,
FreqItems3020[index].R));
}
/* Change BBP setting during switch from a->g, g->a */
if (Channel <= 14)
{
UINT32 TxPinCfg = 0x00050F0A; /* 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
if (IS_RT3352(pAd) || IS_RT5350(pAd))
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x38);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
}
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForG)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 2.4 G band selection PIN */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x04);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
/* Calibration power unbalance issues */
if (pAd->Antenna.field.TxPath == 2)
{
if (pAd->ate.TxAntennaSel == 1)
{
TxPinCfg &= 0xFFFFFFF7;
}
else if (pAd->ate.TxAntennaSel == 2)
{
TxPinCfg &= 0xFFFFFFFD;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
#ifdef A_BAND_SUPPORT
else
{
UINT32 TxPinCfg = 0x00050F05; /* 2007.10.09 by Brian : 0x00050505 ==> 0x00050F05 */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
/* According the Rory's suggestion to solve the middle range issue. */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForA)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue);
ASSERT((BbpValue == 0x04));
/* 5 G band selection PIN, bit1 and bit2 are complement */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
#endif /* A_BAND_SUPPORT */
ATE_CHIP_RX_VGA_GAIN_INIT(pAd);
RtmpOsMsDelay(1);
#ifndef RTMP_RF_RW_SUPPORT
if (Channel <= 14)
{
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%u, Pwr1=%u, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
(pAd->LatchRfRegs.R3 & 0x00003e00) >> 9,
(pAd->LatchRfRegs.R4 & 0x000007c0) >> 6,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
}