VOID RT33xxHaltAction(
IN PRTMP_ADAPTER pAd)
{
UINT32 TxPinCfg = 0x00050F0F;
//
// Turn off LNA_PE or TRSW_POL
//
if (IS_RT3070(pAd) || IS_RT3071(pAd) || IS_RT3390(pAd)||IS_RT3572(pAd))
{
//KH? Both support 3390 usb and PCI
if ((IS_RT3071(pAd) || IS_RT3572(pAd)||IS_RT3390(pAd))
#ifdef RTMP_EFUSE_SUPPORT
&& (pAd->bUseEfuse)
#endif // RTMP_EFUSE_SUPPORT //
)
{
TxPinCfg &= 0xFFFBF0F0; // bit18 off
}
else
{
TxPinCfg &= 0xFFFFF0F0;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
}
/*
==========================================================================
Description:
Load RF sleep-mode setup
==========================================================================
*/
VOID RT33xxLoadRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
// RF_BLOCK_en. RF R1 register Bit 0 to 0
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= (~0x01);
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
// VCO_IC, RF R7 register Bit 4 & Bit 5 to 0
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue &= (~0x30);
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue &= (~0x0E);
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
// RX_CTB_en, RF R21 register Bit 7 to 0
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue &= (~0x80);
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
if (IS_RT3390(pAd))
{
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue |= 0x1D000000;
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
VOID RT30xx_ChipAGCInit(
IN PRTMP_ADAPTER pAd,
IN UCHAR BandWidth)
{
UCHAR R66 = 0x30;
if (pAd->LatchRfRegs.Channel <= 14)
{ /* BG band*/
/* Gary was verified Amazon AP and find that RT307x has BBP_R66 invalid default value */
if (IS_RT3070(pAd)||IS_RT3090(pAd) || IS_RT3390(pAd))
{
R66 = 0x1C + 2*GET_LNA_GAIN(pAd);
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
}
}
else
{
/* A band */
if (BandWidth == BW_20)
{
R66 = (UCHAR)(0x32 + (GET_LNA_GAIN(pAd)*5)/3);
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
}
#ifdef DOT11_N_SUPPORT
else
{
R66 = (UCHAR)(0x3A + (GET_LNA_GAIN(pAd)*5)/3);
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
}
#endif // DOT11_N_SUPPORT //
}
}
VOID RT33xxHaltAction(
IN PRTMP_ADAPTER pAd)
{
UINT32 TxPinCfg = 0x00050F0F;
//
// Turn off LNA_PE or TRSW_POL
//
// Fixed suspend leakage current
// According to MAC 0x0580 bit [31], set MAC 0x1328 bit[18] during suspend mode.
// If SEL_EFUSE=0, set TRSW_POL=0 in suspend mode.
// If SEL_EFUSE=1, set TRSW_POL=1 in suspend mode.
if (IS_RT3390(pAd)
#ifdef RTMP_EFUSE_SUPPORT
&& (pAd->bUseEfuse)
#endif // RTMP_EFUSE_SUPPORT //
)
{
TxPinCfg &= 0xFFFBF0F0; // bit18 off
}
else
{
TxPinCfg &= 0xFFFFF0F0;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
int rtmp_ee_prom_read16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
OUT USHORT *pValue)
{
UINT32 x;
USHORT data;
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
if (pAd->NicConfig2.field.AntDiversity)
{
pAd->EepromAccess = TRUE;
}
#endif
#endif
Offset /= 2;
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)))
{
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
data = ShiftInBits(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
if ((pAd->NicConfig2.field.AntDiversity))
{
pAd->EepromAccess = FALSE;
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
}
#endif
#endif
*pValue = data;
return NDIS_STATUS_SUCCESS;
}
// IRQL = PASSIVE_LEVEL
int rtmp_ee_prom_read16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
OUT USHORT *pValue)
{
UINT32 x;
USHORT data;
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
if (pAd->NicConfig2.field.AntDiversity)
{
pAd->EepromAccess = TRUE;
}
#endif // ANT_DIVERSITY_SUPPORT //
#endif // RT30xx //
Offset /= 2;
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// patch can not access e-Fuse issue
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)))
{
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
// output the read_opcode and register number in that order
ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
// Antenna and EEPROM access are both using EESK pin,
// Therefor we should avoid accessing EESK at the same time
// Then restore antenna after EEPROM access
if ((pAd->NicConfig2.field.AntDiversity)/* || (pAd->RfIcType == RFIC_3020)*/)
{
pAd->EepromAccess = FALSE;
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
}
#endif // ANT_DIVERSITY_SUPPORT //
#endif // RT30xx //
*pValue = data;
return NDIS_STATUS_SUCCESS;
}
/*
========================================================================
Routine Description:
Initialize RT35xx.
Arguments:
pAd - WLAN control block pointer
Return Value:
None
Note:
========================================================================
*/
VOID RT33xx_Init(
IN PRTMP_ADAPTER pAd)
{
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
RTMP_CHIP_CAP *pChipCap = &pAd->chipCap;
/* init capability */
/*
WARNING:
Currently following table are shared by all RT30xx based IC, change it carefully when you add a new IC here.
*/
pChipCap->pRFRegTable = RT3020_RFRegTable;
pChipCap->MaxNumOfBbpId = 185;
/* init operator */
if (IS_RT3390(pAd))
{
#ifdef RT3370
if (pAd->infType == RTMP_DEV_INF_USB)
{
pChipCap->pRFRegTable = RT3370_RFRegTable;
pChipCap->pBBPRegTable = RT3370_BBPRegTable;
pChipCap->bbpRegTbSize = RT3370_NUM_BBP_REG_PARMS;
pChipOps->AsicRfInit = NICInitRT3370RFRegisters;
}
#endif /* RT3370 */
pChipOps->AsicHaltAction = RT33xxHaltAction;
pChipOps->AsicRfTurnOff = RT33xxLoadRFSleepModeSetup;
pChipOps->AsicReverseRfFromSleepMode = RT33xxReverseRFSleepModeSetup;
pChipOps->ChipSwitchChannel = RT33xx_ChipSwitchChannel;
pChipOps->ChipBBPAdjust = RT30xx_ChipBBPAdjust;
pChipOps->RTMPSetAGCInitValue = RT30xx_RTMPSetAGCInitValue;
pChipOps->SetRxAnt = RT33xxSetRxAnt;
pChipOps->ChipResumeMsduTransmission = NULL;
pChipOps->VdrTuning1 = NULL;
pChipOps->RxSensitivityTuning = NULL;
pChipCap->MaxNumOfBbpId = 185;
#ifdef RTMP_FREQ_CALIBRATION_SUPPORT
#ifdef CONFIG_STA_SUPPORT
pChipOps->AsicFreqCalInit = InitFrequencyCalibration;
pChipOps->AsicFreqCalStop = StopFrequencyCalibration;
pChipOps->AsicFreqCal = FrequencyCalibration;
pChipOps->AsicFreqOffsetGet = GetFrequencyOffset;
#endif /* CONFIG_STA_SUPPORT */
#endif /* RTMP_FREQ_CALIBRATION_SUPPORT */
}
}
int rtmp_ee_prom_write16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
IN USHORT Data)
{
UINT32 x;
#ifdef RT30xx
#endif // RT30xx //
Offset /= 2;
EWEN(pAd);
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// patch can not access e-Fuse issue
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)))
{
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
// output the read_opcode ,register number and data in that order
ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
ShiftOutBits(pAd, Data, 16); // 16-bit access
// read DO status
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
EEpromCleanup(pAd);
RTMPusecDelay(10000); //delay for twp(MAX)=10ms
EWDS(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#endif // RT30xx //
return NDIS_STATUS_SUCCESS;
}
/*
==========================================================================
Description:
Reverse RF sleep-mode setup
==========================================================================
*/
VOID RT30xxReverseRFSleepModeSetup(
IN PRTMP_ADAPTER pAd,
IN BOOLEAN FlgIsInitState)
{
UCHAR RFValue;
UINT32 MACValue;
if(!IS_RT3572(pAd))
{
/* RF_BLOCK_en, RF R1 register Bit 0 to 1*/
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue |= 0x01;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
/* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1*/
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue |= 0x20;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
/* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1*/
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue |= 0x0E;
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
/* RX_CTB_en, RF R21 register Bit 7 to 1*/
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72*/
IS_RT3390(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
if ((pAd->MACVersion & 0xffff) < 0x0211)
RFValue = (RFValue & (~0x77)) | 0x3;
else
RFValue = (RFValue & (~0x77));
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
}
/* RT3071 version E has fixed this issue*/
}
}
VOID RT33xxSetRxAnt(
IN PRTMP_ADAPTER pAd,
IN UCHAR Ant)
{
UINT32 Value;
UINT32 x;
if (/*(!pAd->NicConfig2.field.AntDiversity) ||*/
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) ||
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) ||
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) ||
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
{
return;
}
/* the antenna selection is through firmware and MAC register(GPIO3)*/
if (IS_RT3390(pAd) && pAd->RfIcType == RFIC_3320)
{
if (Ant == 0)
{
/* Main antenna*/
/* E2PROM_CSR only in PCI bus Reg., USB Bus need MCU commad to control the EESK pin.*/
#ifdef RTMP_MAC_USB
AsicSendCommandToMcu(pAd, 0x73, 0xff, 0x1, 0x0);
#endif /* RTMP_MAC_USB */
RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
Value &= ~(0x0808);
RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
DBGPRINT(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to main antenna\n"));
}
else
{
/* Aux antenna*/
/* E2PROM_CSR only in PCI bus Reg., USB Bus need MCU commad to control the EESK pin.*/
#ifdef RTMP_MAC_USB
AsicSendCommandToMcu(pAd, 0x73, 0xff, 0x0, 0x0);
#endif /* RTMP_MAC_USB */
RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
Value &= ~(0x0808);
Value |= 0x08;
RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
DBGPRINT(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to aux antenna\n"));
}
}
}
VOID InitFrequencyCalibration(
IN PRTMP_ADAPTER pAd)
{
BBP_R179_STRUC BbpR179 = {{0}};
BBP_R180_STRUC BbpR180 = {{0}};
BBP_R182_STRUC BbpR182 = {{0}};
if (pAd->FreqCalibrationCtrl.bEnableFrequencyCalibration == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("---> %s\n", __FUNCTION__));
/* Initialize the RX_END_STATUS (1) for "Rx OFDM/CCK frequency offset report"*/
if (IS_RT5390(pAd))
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R142, 1);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R143, BBP_R57); /* Rx OFDM/CCK frequency offset report*/
}
else if (IS_RT3390(pAd))
{
/* Initialize the RX_END_STATUS (1, 5) for "Rx OFDM/CCK frequency offset report"*/
BbpR179.field.DataIndex1 = 1;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R179, BbpR179.byte);
BbpR180.field.DataIndex2 = 5;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, BbpR180.byte);
BbpR182.field.DataArray = BBP_R57; /* Rx OFDM/CCK frequency offset report*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, BbpR182.byte);
}
else
{
DBGPRINT(RT_DEBUG_ERROR, ("%s: Not support IC type (MACVersion = 0x%X)\n", __FUNCTION__, pAd->MACVersion));
}
StopFrequencyCalibration(pAd);
DBGPRINT(RT_DEBUG_TRACE, ("%s: frequency offset in the EEPROM = %ld\n",
__FUNCTION__,
pAd->RfFreqOffset));
DBGPRINT(RT_DEBUG_TRACE, ("<--- %s\n", __FUNCTION__));
}
}
/*
==========================================================================
Description:
Load RF sleep-mode setup
==========================================================================
*/
VOID RT33xxLoadRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
{
// RF_BLOCK_en. RF R1 register Bit 0 to 0
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= (~0x01);
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
// VCO_IC, RF R7 register Bit 4 & Bit 5 to 0
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue &= (~0x30);
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue &= (~0x0E);
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
// RX_CTB_en, RF R21 register Bit 7 to 0
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue &= (~0x80);
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72
IS_RT3572(pAd) ||
IS_RT3390(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
RFValue |= 0x77;
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
}
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue |= 0x1D000000;
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
/*
==========================================================================
Description:
Reverse RF sleep-mode setup
==========================================================================
*/
VOID RT33xxReverseRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
// RF_BLOCK_en, RF R1 register Bit 0 to 1
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue |= 0x01;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
// VCO_IC, RF R7 register Bit 4 & Bit 5 to 1
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue |= 0x30;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue |= 0x0E;
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
// RX_CTB_en, RF R21 register Bit 7 to 1
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
if (IS_RT3390(pAd))
{
// RT3071 version E has fixed this issue
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
// patch tx EVM issue temporarily
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
else
{
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
}
/*
==========================================================================
Description:
Reverse RF sleep-mode setup
==========================================================================
*/
VOID RT33xxReverseRFSleepModeSetup(
IN PRTMP_ADAPTER pAd,
IN BOOLEAN FlgIsInitState)
{
UCHAR RFValue;
UINT32 MACValue;
/* RF_BLOCK_en, RF R1 register Bit 0 to 1*/
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue |= 0x01;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
/* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1*/
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
/* According to HK's comment for Max Input power issue.
RF 07 must set to 0x60. */
RFValue |= 0x20; /* 0x30. */
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
/* RX_CTB_en, RF R21 register Bit 7 to 1*/
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
if (IS_RT3390(pAd))
{
/* RT3071 version E has fixed this issue*/
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
/* patch tx EVM issue temporarily*/
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
else
{
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
}
// IRQL = PASSIVE_LEVEL
int rtmp_ee_prom_read16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
OUT USHORT *pValue)
{
UINT32 x;
USHORT data;
#ifdef RT30xx
#endif // RT30xx //
Offset /= 2;
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// patch can not access e-Fuse issue
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)))
{
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
// output the read_opcode and register number in that order
ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#endif // RT30xx //
*pValue = data;
return NDIS_STATUS_SUCCESS;
}
VOID RT30xx_RTMPSetAGCInitValue(
IN PRTMP_ADAPTER pAd,
IN UCHAR BandWidth)
{
UCHAR R66 = 0x30;
if (pAd->LatchRfRegs.Channel <= 14)
{ /* BG band*/
/* Gary was verified Amazon AP and find that RT307x has BBP_R66 invalid default value */
if (IS_RT3070(pAd)||IS_RT3090(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd))
{
R66 = 0x1C + 2*GET_LNA_GAIN(pAd);
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
}
}
}
}
VOID RtmpChipOpsRFHook(
IN RTMP_ADAPTER *pAd)
{
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
pChipOps->pRFRegTable = NULL;
pChipOps->AsicRfInit = NULL;
pChipOps->AsicRfTurnOn = NULL;
pChipOps->AsicRfTurnOff = NULL;
pChipOps->AsicReverseRfFromSleepMode = NULL;
pChipOps->AsicHaltAction = NULL;
#ifdef RT33xx
if (IS_RT3390(pAd) && (pAd->infType == RTMP_DEV_INF_PCI))
{
pChipOps->pRFRegTable = RFRegTableOverRT3390;
pChipOps->AsicHaltAction = RT33xxHaltAction;
pChipOps->AsicRfTurnOff = RT33xxLoadRFSleepModeSetup;
pChipOps->AsicRfInit = NICInitRT3390RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT33xxReverseRFSleepModeSetup;
}
#else // RT33xx //
/* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
#ifdef RT30xx
if (IS_RT30xx(pAd))
{
pChipOps->pRFRegTable = RT30xx_RFRegTable;
pChipOps->AsicHaltAction = RT30xxHaltAction;
#ifdef RT3090
if (IS_RT3090(pAd) && (pAd->infType == RTMP_DEV_INF_PCI))
{
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->AsicRfInit = NICInitRT3090RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup;
}
#endif // RT3090 //
}
#endif // RT30xx //
#endif // RT33xx //
}
VOID RtmpChipOpsRFHook(
IN RTMP_ADAPTER *pAd)
{
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
pChipOps->pRFRegTable = NULL;
pChipOps->AsicRfInit = NULL;
pChipOps->AsicRfTurnOn = NULL;
pChipOps->AsicRfTurnOff = NULL;
pChipOps->AsicReverseRfFromSleepMode = NULL;
pChipOps->AsicHaltAction = NULL;
#ifdef RT33xx
if (IS_RT3390(pAd) && (pAd->infType == RTMP_DEV_INF_PCI))
{
pChipOps->pRFRegTable = RFRegTableOverRT3390;
pChipOps->AsicHaltAction = RT33xxHaltAction;
pChipOps->AsicRfTurnOff = RT33xxLoadRFSleepModeSetup;
pChipOps->AsicRfInit = NICInitRT3390RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT33xxReverseRFSleepModeSetup;
}
#else
#ifdef RT30xx
if (IS_RT30xx(pAd))
{
pChipOps->pRFRegTable = RT30xx_RFRegTable;
pChipOps->AsicHaltAction = RT30xxHaltAction;
#ifdef RT3090
if (IS_RT3090(pAd) && (pAd->infType == RTMP_DEV_INF_PCI))
{
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->AsicRfInit = NICInitRT3090RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup;
}
#endif
}
#endif
#endif
}
void RTMPInitPCIeLinkCtrlValue(struct rt_rtmp_adapter *pAd)
{
int pos;
u16 reg16, data2, PCIePowerSaveLevel, Configuration;
u32 MacValue;
BOOLEAN bFindIntel = FALSE;
struct os_cookie *pObj;
pObj = (struct os_cookie *)pAd->OS_Cookie;
if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
return;
DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
/* Init EEPROM, and save settings */
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))) {
RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
pAd->PCIePowerSaveLevel = PCIePowerSaveLevel & 0xff;
pAd->LnkCtrlBitMask = 0;
if ((PCIePowerSaveLevel & 0xff) == 0xff) {
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_PCIE_DEVICE);
DBGPRINT(RT_DEBUG_TRACE,
("====> PCIePowerSaveLevel = 0x%x.\n",
PCIePowerSaveLevel));
return;
} else {
PCIePowerSaveLevel &= 0x3;
RT28xx_EEPROM_READ16(pAd, 0x24, data2);
if (!
(((data2 & 0xff00) == 0x9200)
&& ((data2 & 0x80) != 0))) {
if (PCIePowerSaveLevel > 1)
PCIePowerSaveLevel = 1;
}
DBGPRINT(RT_DEBUG_TRACE,
("====> Write 0x83 = 0x%x.\n",
PCIePowerSaveLevel));
AsicSendCommandToMcu(pAd, 0x83, 0xff,
(u8)PCIePowerSaveLevel, 0x00);
RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
PCIePowerSaveLevel &= 0xff;
PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
switch (PCIePowerSaveLevel) {
case 0: /* Only support L0 */
pAd->LnkCtrlBitMask = 0;
break;
case 1: /* Only enable L0s */
pAd->LnkCtrlBitMask = 1;
break;
case 2: /* enable L1, L0s */
pAd->LnkCtrlBitMask = 3;
break;
case 3: /* sync with host clk and enable L1, L0s */
pAd->LnkCtrlBitMask = 0x103;
break;
}
RT28xx_EEPROM_READ16(pAd, 0x24, data2);
if ((PCIePowerSaveLevel & 0xff) != 0xff) {
PCIePowerSaveLevel &= 0x3;
if (!
(((data2 & 0xff00) == 0x9200)
&& ((data2 & 0x80) != 0))) {
if (PCIePowerSaveLevel > 1)
PCIePowerSaveLevel = 1;
}
DBGPRINT(RT_DEBUG_TRACE,
("====> rt28xx Write 0x83 Command = 0x%x.\n",
PCIePowerSaveLevel));
AsicSendCommandToMcu(pAd, 0x83, 0xff,
(u8)PCIePowerSaveLevel,
0x00);
}
DBGPRINT(RT_DEBUG_TRACE,
("====> LnkCtrlBitMask = 0x%x.\n",
pAd->LnkCtrlBitMask));
}
} else if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) {
/*
==========================================================================
Description:
Reverse RF sleep-mode setup
==========================================================================
*/
VOID RT30xxReverseRFSleepModeSetup(
IN PRTMP_ADAPTER pAd,
IN BOOLEAN FlgIsInitState)
{
UCHAR RFValue;
UINT32 MACValue;
if(!IS_RT3572(pAd))
{
{
/* RF_BLOCK_en, RF R1 register Bit 0 to 1*/
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue |= 0x01;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
/* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1*/
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue |= 0x20;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
/* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1*/
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue |= 0x0E;
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
/* RX_CTB_en, RF R21 register Bit 7 to 1*/
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
}
if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72*/
IS_RT3572(pAd) ||
IS_RT3390(pAd) ||
IS_RT3593(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
if ((!IS_RT3572(pAd)) && (!IS_RT3593(pAd)))
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
if ((pAd->MACVersion & 0xffff) < 0x0211)
RFValue = (RFValue & (~0x77)) | 0x3;
else
RFValue = (RFValue & (~0x77));
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
}
/* RT3071 version E has fixed this issue*/
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
/* patch tx EVM issue temporarily*/
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd)))
{
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
if(IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, 0x80);
}
VOID RT30xx_ChipSwitchChannel(
IN PRTMP_ADAPTER pAd,
IN UCHAR Channel,
IN BOOLEAN bScan)
{
CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/
UCHAR index;
UINT32 Value = 0; /*BbpReg, Value;*/
UCHAR RFValue;
UINT32 i = 0;
UCHAR Tx0FinePowerCtrl = 0, Tx1FinePowerCtrl = 0;
BBP_R109_STRUC BbpR109 = {{0}};
i = i; /* avoid compile warning */
RFValue = 0;
/* Search Tx power value*/
/*
We can't use ChannelList to search channel, since some central channl's txpowr doesn't list
in ChannelList, so use TxPower array instead.
*/
for (index = 0; index < MAX_NUM_OF_CHANNELS; index++)
{
if (Channel == pAd->TxPower[index].Channel)
{
TxPwer = pAd->TxPower[index].Power;
TxPwer2 = pAd->TxPower[index].Power2;
#ifdef RT33xx
#endif /* RT33xx */
break;
}
}
if (index == MAX_NUM_OF_CHANNELS)
{
DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel));
}
#ifdef RT30xx
/* The RF programming sequence is difference between 3xxx and 2xxx*/
if ((IS_RT30xx(pAd)) &&
((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) ||
(pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) || (pAd->RfIcType == RFIC_3320)))
{
/* modify by WY for Read RF Reg. error */
UCHAR calRFValue;
for (index = 0; index < NUM_OF_3020_CHNL; index++)
{
if (Channel == FreqItems3020[index].Channel)
{
/* Programming channel parameters*/
RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3020[index].N);
/*
RT3370/RT3390 RF version is 0x3320 RF_R3 [7:4] is not reserved bits
RF_R3[6:4] (pa1_bc_cck) : PA1 Bias CCK
RF_R3[7] (pa2_cc_cck) : PA2 Cascode Bias CCK
*/
RT30xxReadRFRegister(pAd, RF_R03, (PUCHAR)(&RFValue));
RFValue = (RFValue & 0xF0) | (FreqItems3020[index].K & ~0xF0); /* <bit 3:0>:K<bit 3:0>*/
RT30xxWriteRFRegister(pAd, RF_R03, RFValue);
RT30xxReadRFRegister(pAd, RF_R06, &RFValue);
RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
RT30xxWriteRFRegister(pAd, RF_R06, RFValue);
/* Set Tx0 Power*/
RT30xxReadRFRegister(pAd, RF_R12, &RFValue);
RFValue = (RFValue & 0xE0) | TxPwer;
RT30xxWriteRFRegister(pAd, RF_R12, RFValue);
/*Set Tx1 Power*/
RT30xxReadRFRegister(pAd, RF_R13, &RFValue);
RFValue = (RFValue & 0xE0) | TxPwer2;
RT30xxWriteRFRegister(pAd, RF_R13, RFValue);
#ifdef RT33xx
#endif /* RT33xx */
/* Tx/Rx Stream setting*/
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= 0x03; /*clear bit[7~2]*/
if (pAd->Antenna.field.TxPath == 1)
RFValue |= 0xA0;
else if (pAd->Antenna.field.TxPath == 2)
RFValue |= 0x80;
if (pAd->Antenna.field.RxPath == 1)
RFValue |= 0x50;
else if (pAd->Antenna.field.RxPath == 2)
RFValue |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
/* Set RF offset*/
RT30xxReadRFRegister(pAd, RF_R23, &RFValue);
RFValue = (RFValue & 0x80) | pAd->RfFreqOffset;
RT30xxWriteRFRegister(pAd, RF_R23, RFValue);
/* Set BW*/
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
{
calRFValue = pAd->Mlme.CaliBW40RfR24;
}
else
{
calRFValue = pAd->Mlme.CaliBW20RfR24;
}
/*
RT3370/RT3390 RF version is 0x3320 RF_R24 [7:6] is not reserved bits
RF_R24[6] (BB_Rx1_out_en) : enable baseband output and ADC input
RF_R24[7] (BB_Tx1_out_en) : enable DAC output or baseband input
*/
RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RFValue));
calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0>*/
RT30xxWriteRFRegister(pAd, RF_R24, calRFValue);
/*
RT3370/RT3390 RF version is 0x3320 RF_R31 [7:6] is not reserved bits
RF_R31[4:0] (rx_agc_fc) : capacitor control in baseband filter
RF_R31[5] (rx_ h20M) : rx_ h20M: 0=10 MHz and 1=20MHz
RF_R31[7:6] (drv_bc_cck) : Driver Bias CCK
*/
/* Set BW*/
if (IS_RT3390(pAd)) /* RT3390 has different AGC for Tx and Rx*/
{
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
{
calRFValue = pAd->Mlme.CaliBW40RfR31;
}
else
{
calRFValue = pAd->Mlme.CaliBW20RfR31;
}
}
RT30xxReadRFRegister(pAd, RF_R31, (PUCHAR)(&RFValue));
calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:rx_h20M<bit 5> and <bit 4:0>:rx_agc_fc<bit 4:0>*/
RT30xxWriteRFRegister(pAd, RF_R31, calRFValue);
/* Enable RF tuning*/
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue = RFValue | 0x1;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
/* latch channel for future usage.*/
pAd->LatchRfRegs.Channel = Channel;
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
Channel,
pAd->RfIcType,
TxPwer,
TxPwer2,
pAd->Antenna.field.TxPath,
FreqItems3020[index].N,
FreqItems3020[index].K,
FreqItems3020[index].R));
break;
}
}
}
else
#endif /* RT30xx */
{
switch (pAd->RfIcType)
{
default:
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n",
Channel, pAd->RfIcType));
break;
}
}
/* Change BBP setting during siwtch from a->g, g->a*/
if (Channel <= 14)
{
ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/
/* Rx High power VGA offset for LNA select*/
{
if (pAd->NicConfig2.field.ExternalLNAForG)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x04);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
else
{
ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/
UINT8 bbpValue;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/
/* Set the BBP_R82 value here */
bbpValue = 0xF2;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue);
/* Rx High power VGA offset for LNA select*/
if (pAd->NicConfig2.field.ExternalLNAForA)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R*/
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
/* R66 should be set according to Channel and use 20MHz when scanning*/
if (bScan)
RTMPSetAGCInitValue(pAd, BW_20);
else
RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW);
/*
On 11A, We should delay and wait RF/BBP to be stable
and the appropriate time should be 1000 micro seconds
2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.
*/
RTMPusecDelay(1000);
}
VOID NICInitRT3370RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
UINT8 RfReg = 0;
UINT32 data;
CHAR bbpreg;
/* Driver must read EEPROM to get RfIcType before initial RF registers*/
/* Initialize RF register to default value*/
/* Init RF calibration*/
/* Driver should toggle RF R30 bit7 before init RF registers*/
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
for (i = 0; i < RT3370_NUM_RF_REG_PARMS; i++)
{
RT30xxWriteRFRegister(pAd, RT3370_RFRegTable[i].Register, RT3370_RFRegTable[i].Value);
}
/* Driver should set RF R6 bit6 on before init RF registers */
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
/* RT3071 version E has fixed this issue*/
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
/* patch tx EVM issue temporarily*/
RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
}
else
{
/* patch CCK ok, OFDM failed issue, just toggle and restore LDO_CFG0.*/
RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
RTMPusecDelay(1000);
data = ((data & 0xE0FFFFFF) | 0x01000000);
RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
}
/* patch LNA_PE_G1 failed issue*/
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
if (IS_RT3390(pAd)) /* Disable RF filter calibration*/
{
pAd->Mlme.CaliBW20RfR24 = BW20RFR24;
pAd->Mlme.CaliBW40RfR24 = BW40RFR24;
pAd->Mlme.CaliBW20RfR31 = BW20RFR31;
pAd->Mlme.CaliBW40RfR31 = BW40RFR31;
}
else
{
/*For RF filter Calibration*/
/*RTMPFilterCalibration(pAd);*/
}
/* set led open drain enable*/
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
/* set default antenna as main*/
if (pAd->RfIcType == RFIC_3320)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
/*
From RT3071 Power Sequence v1.1 document, the Normal Operation Setting Registers as follow :
BBP_R138 / RF_R1 / RF_R15 / RF_R17 / RF_R20 / RF_R21.
*/
/* add by johnli, RF power sequence setup, load RF normal operation-mode setup*/
RT33xxLoadRFNormalModeSetup(pAd);
}
VOID RTMPInitPCIeLinkCtrlValue(
IN PRTMP_ADAPTER pAd)
{
INT pos;
USHORT reg16, data2, PCIePowerSaveLevel, Configuration;
UINT32 MacValue;
BOOLEAN bFindIntel = FALSE;
POS_COOKIE pObj;
pObj = (POS_COOKIE) pAd->OS_Cookie;
if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
{
DBGPRINT(RT_DEBUG_TRACE, ("Not PCIe device.\n"));
return;
}
DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __FUNCTION__));
// Init EEPROM, and save settings
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)))
{
RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
pAd->PCIePowerSaveLevel = PCIePowerSaveLevel & 0xff;
pAd->LnkCtrlBitMask = 0;
if ((PCIePowerSaveLevel&0xff) == 0xff)
{
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE);
DBGPRINT(RT_DEBUG_TRACE, ("====> PCIePowerSaveLevel = 0x%x.\n", PCIePowerSaveLevel));
return;
}
else
{
PCIePowerSaveLevel &= 0x3;
RT28xx_EEPROM_READ16(pAd, 0x24, data2);
if( !(((data2&0xff00) == 0x9200) && ((data2&0x80) !=0)) )
{
if (PCIePowerSaveLevel > 1 )
PCIePowerSaveLevel = 1;
}
DBGPRINT(RT_DEBUG_TRACE, ("====> Write 0x83 = 0x%x.\n", PCIePowerSaveLevel));
AsicSendCommandToMcu(pAd, TRUE, 0x83, 0xff, (UCHAR)PCIePowerSaveLevel, 0x00);
RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
PCIePowerSaveLevel &= 0xff;
PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
switch(PCIePowerSaveLevel)
{
case 0: // Only support L0
pAd->LnkCtrlBitMask = 0;
break;
case 1: // Only enable L0s
pAd->LnkCtrlBitMask = 1;
break;
case 2: // enable L1, L0s
pAd->LnkCtrlBitMask = 3;
break;
case 3: // sync with host clk and enable L1, L0s
pAd->LnkCtrlBitMask = 0x103;
break;
}
RT28xx_EEPROM_READ16(pAd, 0x24, data2);
if ((PCIePowerSaveLevel&0xff) != 0xff)
{
PCIePowerSaveLevel &= 0x3;
if( !(((data2&0xff00) == 0x9200) && ((data2&0x80) !=0)) )
{
if (PCIePowerSaveLevel > 1 )
PCIePowerSaveLevel = 1;
}
DBGPRINT(RT_DEBUG_TRACE, ("====> rt28xx Write 0x83 Command = 0x%x.\n", PCIePowerSaveLevel));
printk("\n\n\n%s:%d\n",__FUNCTION__,__LINE__);
AsicSendCommandToMcu(pAd, TRUE, 0x83, 0xff, (UCHAR)PCIePowerSaveLevel, 0x00);
}
DBGPRINT(RT_DEBUG_TRACE, ("====> LnkCtrlBitMask = 0x%x.\n", pAd->LnkCtrlBitMask));
}
}
/*
==========================================================================
Description:
Reverse RF sleep-mode setup
==========================================================================
*/
VOID RT30xxReverseRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
if(!IS_RT3572(pAd))
{
#ifdef RT53xx
if (IS_RT5390(pAd))
{
UCHAR rfreg;
RT30xxReadRFRegister(pAd, RF_R01, &rfreg);
if (IS_RT5392(pAd))
{
rfreg = ((rfreg & ~0x3F) | 0x3F);
}
else
{
rfreg = ((rfreg & ~0x0F) | 0x0F); // Enable rf_block_en, pll_en, rx0_en and tx0_en
}
RT30xxWriteRFRegister(pAd, RF_R01, rfreg);
RT30xxReadRFRegister(pAd, RF_R06, &rfreg);
if (IS_RT5390F(pAd) || IS_RT5392C(pAd))
{
rfreg = ((rfreg & ~0xC0) | 0xC0); // vco_ic (VCO bias current control, 11: high)
}
else
{
rfreg = ((rfreg & ~0xC0) | 0x80); // vco_ic (VCO bias current control, 10: mid.)
}
RT30xxWriteRFRegister(pAd, RF_R06, rfreg);
if (!IS_RT5392(pAd))
{
RT30xxReadRFRegister(pAd, RF_R02, &rfreg);
rfreg = ((rfreg & ~0x80) | 0x80); // rescal_en (initiate calibration)
RT30xxWriteRFRegister(pAd, RF_R02, rfreg);
}
RT30xxReadRFRegister(pAd, RF_R22, &rfreg);
rfreg = ((rfreg & ~0xE0) | 0x20); // cp_ic (reference current control, 001: 0.33 mA)
RT30xxWriteRFRegister(pAd, RF_R22, rfreg);
RT30xxReadRFRegister(pAd, RF_R42, &rfreg);
rfreg = ((rfreg & ~0x40) | 0x40); // rx_ctb_en
RT30xxWriteRFRegister(pAd, RF_R42, rfreg);
RT30xxReadRFRegister(pAd, RF_R20, &rfreg);
rfreg = ((rfreg & ~0x77) | 0x00); // ldo_rf_vc and ldo_pll_vc ( 111: +0.15)
RT30xxWriteRFRegister(pAd, RF_R20, rfreg);
RT30xxReadRFRegister(pAd, RF_R03, &rfreg);
rfreg = ((rfreg & ~0x80) | 0x80); // vcocal_en (initiate VCO calibration (reset after completion))
RT30xxWriteRFRegister(pAd, RF_R03, rfreg);
}
else
#endif // RT53xx //
{
// RF_BLOCK_en, RF R1 register Bit 0 to 1
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue |= 0x01;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
// VCO_IC, RF R7 register Bit 5 to 1 (VCO bias current control, 11: high)
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue |= 0x30;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue |= 0x0E;
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
// RX_CTB_en, RF R21 register Bit 7 to 1
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
}
if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72
IS_RT3572(pAd) ||
IS_RT3390(pAd) ||
IS_RT3593(pAd) ||
IS_RT5390(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
if ((!IS_RT3572(pAd)) && (!IS_RT3593(pAd)) && (!IS_RT5390(pAd)) && (!IS_RT3390(pAd)) && (!IS_RT3090(pAd)))
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
if ((pAd->MACVersion & 0xffff) < 0x0211)
RFValue = (RFValue & (~0x77)) | 0x3;
else
RFValue = (RFValue & (~0x77));
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
}
// RT3071 version E has fixed this issue
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
// patch tx EVM issue temporarily
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
// else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd)) || (pAd->CommonCfg.PatchHWControl.field.LDOCfg == 1))
else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd) && !IS_RT5390(pAd)))
{
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
if(IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, 0x80);
}
/*
==========================================================================
Description:
Load RF sleep-mode setup
==========================================================================
*/
VOID RT30xxLoadRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
if(!IS_RT3572(pAd))
{
#ifdef RT53xx
if (IS_RT5390(pAd))
{
UCHAR rfreg;
RT30xxReadRFRegister(pAd, RF_R01, &rfreg);
rfreg = ((rfreg & ~0x01) | 0x00); // vco_en
RT30xxWriteRFRegister(pAd, RF_R01, rfreg);
RT30xxReadRFRegister(pAd, RF_R06, &rfreg);
rfreg = ((rfreg & ~0xC0) | 0x00); // vco_ic (VCO bias current control, 00: off)
RT30xxWriteRFRegister(pAd, RF_R06, rfreg);
RT30xxReadRFRegister(pAd, RF_R22, &rfreg);
rfreg = ((rfreg & ~0xE0) | 0x00); // cp_ic (reference current control, 000: 0.25 mA)
RT30xxWriteRFRegister(pAd, RF_R22, rfreg);
RT30xxReadRFRegister(pAd, RF_R42, &rfreg);
rfreg = ((rfreg & ~0x40) | 0x00); // rx_ctb_en
RT30xxWriteRFRegister(pAd, RF_R42, rfreg);
/*
RT30xxReadRFRegister(pAd, RF_R20, &rfreg);
rfreg = ((rfreg & ~0x77) | 0x77); // ldo_pll_vc and ldo_rf_vc (111: -0.15)
RT30xxWriteRFRegister(pAd, RF_R20, rfreg);
*/
}
else
#endif // RT53xx //
{
// RF_BLOCK_en. RF R1 register Bit 0 to 0
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= (~0x01);
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
// VCO_IC, RF R7 register Bit 4 & Bit 5 to 0
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue &= (~0x30);
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue &= (~0x0E);
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
// RX_CTB_en, RF R21 register Bit 7 to 0
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue &= (~0x80);
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
}
// Don't touch LDO_CFG0 for 3090F & 3593, possibly the board is single power scheme
if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72
IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT5390(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
if (!IS_RT3572(pAd) && !IS_RT3390(pAd) && !IS_RT5390(pAd) && !IS_RT3090(pAd))
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
RFValue |= 0x77;
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue |= 0x1D000000;
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
}
VOID NICInitRT3370RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
// Driver must read EEPROM to get RfIcType before initial RF registers
// Initialize RF register to default value
if (IS_RT3090(pAd)||IS_RT3390(pAd)||IS_RT3572(pAd))
{
// Init RF calibration
// Driver should toggle RF R30 bit7 before init RF registers
UINT32 RfReg = 0, data;
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
// init R24, R31
RT30xxWriteRFRegister(pAd, RF_R24, 0x0F);
RT30xxWriteRFRegister(pAd, RF_R31, 0x0F);
if (IS_RT3390(pAd))
{
// patch LNA_PE_G1 failed issue
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
// RF registers initialization
for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++)
{
RT30xxWriteRFRegister(pAd, RFRegTableOverRT3390[i].Register, RFRegTableOverRT3390[i].Value);
}
}
// patch LNA_PE_G1 failed issue
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
// Initialize RF register to default value
for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++)
{
RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value);
}
// Driver should set RF R6 bit6 on before calibration
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
//For RF filter Calibration
RTMPFilterCalibration(pAd);
// Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
if ((pAd->MACVersion & 0xffff) < 0x0211)
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
// set led open drain enable
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
// set default antenna as main
if (pAd->RfIcType == RFIC_3020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
// add by johnli, RF power sequence setup, load RF normal operation-mode setup
RT30xxLoadRFNormalModeSetup(pAd);
}
}
RTMP_BUILD_DRV_OPS_FUNCTION_BODY
#endif /* OS_ABL_FUNC_SUPPORT */
#endif /* LINUX */
int rt28xx_init(
IN VOID *pAdSrc,
IN PSTRING pDefaultMac,
IN PSTRING pHostName)
{
PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdSrc;
UINT index;
UCHAR TmpPhy;
NDIS_STATUS Status;
if (pAd == NULL)
return FALSE;
/* reset Adapter flags*/
RTMP_CLEAR_FLAGS(pAd);
/* Init BssTab & ChannelInfo tabbles for auto channel select.*/
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
AutoChBssTableInit(pAd);
ChannelInfoInit(pAd);
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef DOT11_N_SUPPORT
/* Allocate BA Reordering memory*/
if (ba_reordering_resource_init(pAd, MAX_REORDERING_MPDU_NUM) != TRUE)
goto err1;
#endif /* DOT11_N_SUPPORT */
/* Make sure MAC gets ready.*/
index = 0;
if (WaitForAsicReady(pAd) != TRUE)
goto err1;
DBGPRINT(RT_DEBUG_TRACE, ("MAC[Ver:Rev=0x%08x]\n", pAd->MACVersion));
if (MAX_LEN_OF_MAC_TABLE > MAX_AVAILABLE_CLIENT_WCID(pAd))
{
DBGPRINT(RT_DEBUG_ERROR, ("MAX_LEN_OF_MAC_TABLE can not be larger than MAX_AVAILABLE_CLIENT_WCID!!!!\n"));
goto err1;
}
#ifdef RTMP_MAC_PCI
#if defined(RT3090) || defined(RT3592) || defined(RT3390) || defined(RT3593) || defined(RT5390) || defined(RT5392) || defined(RT5592)
/*Iverson patch PCIE L1 issue to make sure that driver can be read,write ,BBP and RF register at pcie L.1 level */
if ((IS_RT3090(pAd) || IS_RT3572(pAd) ||IS_RT3390(pAd) || IS_RT3593(pAd)
|| IS_RT5390(pAd) || IS_RT5392(pAd) || IS_RT5592(pAd))
&&pAd->infType==RTMP_DEV_INF_PCIE)
{
UINT32 MacValue = 0;
RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue);
MacValue |= 0x402;
RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue);
DBGPRINT(RT_DEBUG_TRACE, ("AUX_CTRL = 0x%x\n", MacValue));
}
#endif
/* To fix driver disable/enable hang issue when radio off*/
RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x2);
#endif /* RTMP_MAC_PCI */
/* Disable DMA*/
RT28XXDMADisable(pAd);
/* Load 8051 firmware*/
Status = NICLoadFirmware(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("NICLoadFirmware failed, Status[=0x%08x]\n", Status));
goto err1;
}
NICLoadRateSwitchingParams(pAd);
/* Disable interrupts here which is as soon as possible*/
/* This statement should never be true. We might consider to remove it later*/
#ifdef RTMP_MAC_PCI
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE))
{
RTMP_ASIC_INTERRUPT_DISABLE(pAd);
}
#endif /* RTMP_MAC_PCI */
#ifdef RESOURCE_PRE_ALLOC
Status = RTMPInitTxRxRingMemory(pAd);
#else
Status = RTMPAllocTxRxRingMemory(pAd);
#endif /* RESOURCE_PRE_ALLOC */
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("RTMPAllocTxRxMemory failed, Status[=0x%08x]\n", Status));
goto err2;
}
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
/* initialize MLME*/
Status = RtmpMgmtTaskInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
goto err3;
Status = MlmeInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("MlmeInit failed, Status[=0x%08x]\n", Status));
goto err4;
}
#ifdef RT_SOC_SUPPORT
#ifdef VIDEO_TURBINE_SUPPORT
VideoConfigInit(pAd);
#endif /* VIDEO_TURBINE_SUPPORT */
#endif /* RT_SOC_SUPPORT */
/* Initialize pAd->StaCfg, pAd->ApCfg, pAd->CommonCfg to manufacture default*/
UserCfgInit(pAd);
Status = RtmpNetTaskInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
goto err5;
/* COPY_MAC_ADDR(pAd->ApCfg.MBSSID[apidx].Bssid, netif->hwaddr);*/
/* pAd->bForcePrintTX = TRUE;*/
CfgInitHook(pAd);
#ifdef CONFIG_AP_SUPPORT
if ((pAd->OpMode == OPMODE_AP)
)
APInitialize(pAd);
#endif /* CONFIG_AP_SUPPORT */
#ifdef BLOCK_NET_IF
initblockQueueTab(pAd);
#endif /* BLOCK_NET_IF */
Status = MeasureReqTabInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("MeasureReqTabInit failed, Status[=0x%08x]\n",Status));
goto err6;
}
Status = TpcReqTabInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("TpcReqTabInit failed, Status[=0x%08x]\n",Status));
goto err6;
}
/* Init the hardware, we need to init asic before read registry, otherwise mac register will be reset*/
Status = NICInitializeAdapter(pAd, TRUE);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("NICInitializeAdapter failed, Status[=0x%08x]\n", Status));
if (Status != NDIS_STATUS_SUCCESS)
goto err6;
}
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
}
#endif /* CONFIG_AP_SUPPORT */
/* Read parameters from Config File */
/* unknown, it will be updated in NICReadEEPROMParameters */
pAd->RfIcType = RFIC_UNKNOWN;
Status = RTMPReadParametersHook(pAd);
/* Set eeprom related hook functions */
Status = RtmpChipOpsEepromHook(pAd, pAd->infType);
DBGPRINT(RT_DEBUG_OFF, ("1. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("RTMPReadParametersHook failed, Status[=0x%08x]\n",Status));
goto err6;
}
#ifdef DOT11_N_SUPPORT
/*Init Ba Capability parameters.*/
/* RT28XX_BA_INIT(pAd);*/
pAd->CommonCfg.DesiredHtPhy.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity;
pAd->CommonCfg.DesiredHtPhy.AmsduEnable = (USHORT)pAd->CommonCfg.BACapability.field.AmsduEnable;
pAd->CommonCfg.DesiredHtPhy.AmsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize;
pAd->CommonCfg.DesiredHtPhy.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode;
/* UPdata to HT IE*/
pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode;
pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize;
pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity;
#endif /* DOT11_N_SUPPORT */
/* after reading Registry, we now know if in AP mode or STA mode*/
/* Load 8051 firmware; crash when FW image not existent*/
/* Status = NICLoadFirmware(pAd);*/
/* if (Status != NDIS_STATUS_SUCCESS)*/
/* break;*/
DBGPRINT(RT_DEBUG_OFF, ("2. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
/* We should read EEPROM for all cases. rt2860b*/
NICReadEEPROMParameters(pAd, (PSTRING)pDefaultMac);
DBGPRINT(RT_DEBUG_OFF, ("3. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
#ifdef LED_CONTROL_SUPPORT
/* Send LED Setting to MCU */
RTMPInitLEDMode(pAd);
#endif /* LED_CONTROL_SUPPORT */
NICInitAsicFromEEPROM(pAd); /* rt2860b */
#ifdef RALINK_ATE
if (ATEInit(pAd) != NDIS_STATUS_SUCCESS)
{
DBGPRINT(RT_DEBUG_ERROR, ("%s(): ATE initialization failed !\n", __FUNCTION__));
goto err6;
}
#endif /* RALINK_ATE */
#ifdef RTMP_FREQ_CALIBRATION_SUPPORT
#endif /* RTMP_FREQ_CALIBRATION_SUPPORT */
#ifdef RTMP_INTERNAL_TX_ALC
/* Initialize the desired TSSI table*/
RTMP_CHIP_ASIC_TSSI_TABLE_INIT(pAd);
#endif /* RTMP_INTERNAL_TX_ALC */
#ifdef RTMP_TEMPERATURE_COMPENSATION
/* Temperature compensation, initialize the lookup table */
DBGPRINT(RT_DEBUG_OFF, ("bAutoTxAgcG = %d\n", pAd->bAutoTxAgcG));
if (pAd->chipCap.bTempCompTxALC && pAd->bAutoTxAgcG)
InitLookupTable(pAd);
#endif /* RTMP_TEMPERATURE_COMPENSATION */
#ifdef RTMP_FREQ_CALIBRATION_SUPPORT
#endif /* RTMP_FREQ_CALIBRATION_SUPPORT */
/* Set PHY to appropriate mode*/
TmpPhy = pAd->CommonCfg.PhyMode;
pAd->CommonCfg.PhyMode = 0xff;
RTMPSetPhyMode(pAd, TmpPhy);
#ifdef DOT11_N_SUPPORT
SetCommonHT(pAd);
#endif /* DOT11_N_SUPPORT */
/* No valid channels.*/
if (pAd->ChannelListNum == 0)
{
DBGPRINT(RT_DEBUG_ERROR, ("Wrong configuration. No valid channel found. Check \"ContryCode\" and \"ChannelGeography\" setting.\n"));
goto err6;
}
#ifdef DOT11_N_SUPPORT
DBGPRINT(RT_DEBUG_OFF, ("MCS Set = %02x %02x %02x %02x %02x\n", pAd->CommonCfg.HtCapability.MCSSet[0],
pAd->CommonCfg.HtCapability.MCSSet[1], pAd->CommonCfg.HtCapability.MCSSet[2],
pAd->CommonCfg.HtCapability.MCSSet[3], pAd->CommonCfg.HtCapability.MCSSet[4]));
#endif /* DOT11_N_SUPPORT */
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef AP_QLOAD_SUPPORT
/* init QBSS Element */
QBSS_LoadInit(pAd);
#endif /* AP_QLOAD_SUPPORT */
}
#endif /* CONFIG_AP_SUPPORT */
/* APInitialize(pAd);*/
#ifdef IKANOS_VX_1X0
VR_IKANOS_FP_Init(pAd->ApCfg.BssidNum, pAd->PermanentAddress);
#endif /* IKANOS_VX_1X0 */
#ifdef RALINK_ATE
#ifdef RT5592
#ifdef RTMP_RF_RW_SUPPORT
/* both for RT5572 and RT5592 */
if (IS_RT5592(pAd))
{
RT55x2ATEFilterCalibration(pAd);
}
#endif /* RTMP_RF_RW_SUPPORT */
#endif /* RT5592 */
#endif /* RALINK_ATE */
#ifdef CONFIG_AP_SUPPORT
/* Initialize RF register to default value*/
if (pAd->OpMode == OPMODE_AP)
{
AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
AsicLockChannel(pAd, pAd->CommonCfg.Channel);
}
#endif /* CONFIG_AP_SUPPORT */
/*
Some modules init must be called before APStartUp().
Or APStartUp() will make up beacon content and call
other modules API to get some information to fill.
*/
#ifdef CONFIG_TSO_SUPPORT
if (RTMP_TEST_MORE_FLAG(pAd, fRTMP_ADAPTER_TSO_SUPPORT))
RTMPTsoEnable(pAd);
#endif /* CONFIG_TSO_SUPPORT */
if (pAd && (Status != NDIS_STATUS_SUCCESS))
{
/* Undo everything if it failed*/
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE))
{
/* NdisMDeregisterInterrupt(&pAd->Interrupt);*/
RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
}
/* RTMPFreeAdapter(pAd); we will free it in disconnect()*/
}
else if (pAd)
{
/* Microsoft HCT require driver send a disconnect event after driver initialization.*/
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED);
OPSTATUS_CLEAR_FLAG(pAd, fOP_AP_STATUS_MEDIA_STATE_CONNECTED);
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE);
DBGPRINT(RT_DEBUG_TRACE, ("NDIS_STATUS_MEDIA_DISCONNECT Event B!\n"));
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
if (pAd->ApCfg.bAutoChannelAtBootup || (pAd->CommonCfg.Channel == 0))
{
UINT8 BBPValue = 0;
/* Enable Interrupt first due to we need to scan channel to receive beacons.*/
RTMP_IRQ_ENABLE(pAd);
/* Now Enable RxTx*/
RTMPEnableRxTx(pAd);
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP);
/* Let BBP register at 20MHz to do scan */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
BBPValue &= (~0x18);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
DBGPRINT(RT_DEBUG_ERROR, ("SYNC - BBP R4 to 20MHz.l\n"));
/* Now we can receive the beacon and do the listen beacon*/
/* use default BW to select channel*/
pAd->CommonCfg.Channel = AP_AUTO_CH_SEL(pAd, pAd->ApCfg.AutoChannelAlg);
pAd->ApCfg.bAutoChannelAtBootup = FALSE;
}
#ifdef DOT11_N_SUPPORT
/* If phymode > PHY_11ABGN_MIXED and BW=40 check extension channel, after select channel */
N_ChannelCheck(pAd);
#ifdef DOT11N_DRAFT3
/*
We only do this Overlapping BSS Scan when system up, for the
other situation of channel changing, we depends on station's
report to adjust ourself.
*/
if (pAd->CommonCfg.bForty_Mhz_Intolerant == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("Disable 20/40 BSSCoex Channel Scan(BssCoex=%d, 40MHzIntolerant=%d)\n",
pAd->CommonCfg.bBssCoexEnable,
pAd->CommonCfg.bForty_Mhz_Intolerant));
}
else if(pAd->CommonCfg.bBssCoexEnable == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("Enable 20/40 BSSCoex Channel Scan(BssCoex=%d)\n",
pAd->CommonCfg.bBssCoexEnable));
APOverlappingBSSScan(pAd);
}
RTMP_11N_D3_TimerInit(pAd);
/* RTMPInitTimer(pAd, &pAd->CommonCfg.Bss2040CoexistTimer, GET_TIMER_FUNCTION(Bss2040CoexistTimeOut), pAd, FALSE);*/
#endif /* DOT11N_DRAFT3 */
#endif /* DOT11_N_SUPPORT */
APStartUp(pAd);
DBGPRINT(RT_DEBUG_OFF, ("Main bssid = %02x:%02x:%02x:%02x:%02x:%02x\n",
PRINT_MAC(pAd->ApCfg.MBSSID[BSS0].Bssid)));
}
#endif /* CONFIG_AP_SUPPORT */
}/* end of else*/
/* Set up the Mac address*/
#ifdef CONFIG_AP_SUPPORT
RtmpOSNetDevAddrSet(pAd->OpMode, pAd->net_dev, &pAd->CurrentAddress[0], NULL);
#endif /* CONFIG_AP_SUPPORT */
/* Various AP function init*/
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef MBSS_SUPPORT
/* the function can not be moved to RT2860_probe() even register_netdev()
is changed as register_netdevice().
Or in some PC, kernel will panic (Fedora 4) */
/* RT28xx_MBSS_Init(pAd, pAd->net_dev); os abl move to rt_main_dev.c*/
#endif /* MBSS_SUPPORT */
#ifdef WDS_SUPPORT
/* RT28xx_WDS_Init(pAd, pAd->net_dev);*/
#endif /* WDS_SUPPORT */
#ifdef APCLI_SUPPORT
/* RT28xx_ApCli_Init(pAd, pAd->net_dev);*/
#endif /* APCLI_SUPPORT */
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef UAPSD_SUPPORT
UAPSD_Init(pAd);
#endif /* UAPSD_SUPPORT */
/* assign function pointers*/
#ifdef MAT_SUPPORT
/* init function pointers, used in OS_ABL */
RTMP_MATOpsInit(pAd);
#endif /* MAT_SUPPORT */
#ifdef RT_SOC_SUPPORT
if (pAd->infType == RTMP_DEV_INF_RBUS ||
pAd->infType == RTMP_DEV_INF_PCIE)
{
#ifdef VIDEO_TURBINE_SUPPORT
VideoTurbineDynamicTune(pAd);
#endif /* VIDEO_TURBINE_SUPPORT */
#ifdef RT3XXX_ANTENNA_DIVERSITY_SUPPORT
RT3XXX_AntDiversity_Init(pAd);
#endif /* RT3XXX_ANTENNA_DIVERSITY_SUPPORT */
}
#endif /* RT_SOC_SUPPORT */
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef MAT_SUPPORT
MATEngineInit(pAd);
#endif /* MAT_SUPPORT */
#ifdef CLIENT_WDS
CliWds_ProxyTabInit(pAd);
#endif /* CLIENT_WDS */
}
#endif /* CONFIG_AP_SUPPORT */
/* auto-fall back settings */
RTMP_IO_WRITE32(pAd, HT_FBK_CFG1, 0xedcba980);
#ifdef DOT11N_SS3_SUPPORT
if (pAd->CommonCfg.TxStream >= 3)
{
RTMP_IO_WRITE32(pAd, TX_FBK_CFG_3S_0, 0x12111008);
RTMP_IO_WRITE32(pAd, TX_FBK_CFG_3S_1, 0x16151413);
}
#endif /* DOT11N_SS3_SUPPORT */
#ifdef STREAM_MODE_SUPPORT
RtmpStreamModeInit(pAd);
#endif /* STREAM_MODE_SUPPORT */
#if defined(RT2883) || defined(RT3883) || defined(RT3593)
if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd))
{
UINT8 BBPValue = 0;
BBP_IO_READ8_BY_REG_ID(pAd, BBP_R65, &BBPValue);
if (pAd->CommonCfg.FineAGC)
BBPValue |= 0x40; /* turn on fine AGC*/
else
BBPValue &= ~0x40; /* turn off fine AGC*/
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R65, BBPValue);
}
#endif /* defined(RT2883) || defined(RT3883) || defined(RT3593) */
#ifdef DOT11_N_SUPPORT
#ifdef TXBF_SUPPORT
if (pAd->CommonCfg.ITxBfTimeout)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R179, 0x02);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, 0);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, pAd->CommonCfg.ITxBfTimeout & 0xFF);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, 1);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, (pAd->CommonCfg.ITxBfTimeout>>8) & 0xFF);
}
VOID RtmpChipOpsRFHook(
IN RTMP_ADAPTER *pAd)
{
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
pChipOps->pRFRegTable = NULL;
pChipOps->pBBPRegTable = NULL;
pChipOps->bbpRegTbSize = 0;
pChipOps->AsicRfInit = NULL;
pChipOps->AsicRfTurnOn = NULL;
pChipOps->AsicRfTurnOff = NULL;
pChipOps->AsicReverseRfFromSleepMode = NULL;
pChipOps->AsicHaltAction = NULL;
/* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
#ifdef RT33xx
if (IS_RT3390(pAd))
{
#ifdef RT3390
if (pAd->infType == RTMP_DEV_INF_PCIE)
{
pChipOps->pRFRegTable = RF3320_RFRegTable;
pChipOps->AsicRfInit = NICInitRT3390RFRegisters;
}
#endif // RT3390 //
pChipOps->AsicHaltAction = RT33xxHaltAction;
pChipOps->AsicRfTurnOff = RT33xxLoadRFSleepModeSetup;
pChipOps->AsicReverseRfFromSleepMode = RT33xxReverseRFSleepModeSetup;
}
#endif // RT33xx //
#ifdef RT30xx
if (IS_RT30xx(pAd))
{
/*
WARNING:
Currently following table are shared by all RT30xx based IC, change it carefully when you add a new IC here.
*/
pChipOps->pRFRegTable = RT3020_RFRegTable;
pChipOps->AsicHaltAction = RT30xxHaltAction;
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup;
#ifdef RT3090
if (IS_RT3090(pAd) && (pAd->infType == RTMP_DEV_INF_PCIE))
{
pChipOps->AsicRfInit = NICInitRT3090RFRegisters;
}
#endif // RT3090 //
}
#endif // RT30xx //
DBGPRINT(RT_DEBUG_TRACE, ("Chip specific bbpRegTbSize=%d!\n", pChipOps->bbpRegTbSize));
}
VOID AsicGetAutoAgcOffsetForExternalTxAlc(
IN PRTMP_ADAPTER pAd,
IN PCHAR pDeltaPwr,
IN PCHAR pTotalDeltaPwr,
IN PCHAR pAgcCompensate,
IN PCHAR pDeltaPowerByBbpR1)
{
BBP_R49_STRUC BbpR49;
BOOLEAN bAutoTxAgc = FALSE;
UCHAR TssiRef, *pTssiMinusBoundary, *pTssiPlusBoundary, TxAgcStep, idx;
PCHAR pTxAgcCompensate = NULL;
CHAR DeltaPwr = 0;
DBGPRINT(RT_DEBUG_INFO, ("-->%s\n", __FUNCTION__));
BbpR49.byte = 0;
/* TX power compensation for temperature variation based on TSSI. Try every 4 second */
if (pAd->Mlme.OneSecPeriodicRound % 4 == 0)
{
if (pAd->CommonCfg.Channel <= 14)
{
/* bg channel */
bAutoTxAgc = pAd->bAutoTxAgcG;
TssiRef = pAd->TssiRefG;
pTssiMinusBoundary = &pAd->TssiMinusBoundaryG[0];
pTssiPlusBoundary = &pAd->TssiPlusBoundaryG[0];
TxAgcStep = pAd->TxAgcStepG;
pTxAgcCompensate = &pAd->TxAgcCompensateG;
}
else
{
/* a channel */
bAutoTxAgc = pAd->bAutoTxAgcA;
TssiRef = pAd->TssiRefA;
pTssiMinusBoundary = &pAd->TssiMinusBoundaryA[0];
pTssiPlusBoundary = &pAd->TssiPlusBoundaryA[0];
TxAgcStep = pAd->TxAgcStepA;
pTxAgcCompensate = &pAd->TxAgcCompensateA;
}
if (bAutoTxAgc)
{
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpR49.byte);
/* TSSI representation */
if (IS_RT3071(pAd) || IS_RT3390(pAd) || IS_RT3090A(pAd) || IS_RT3572(pAd)) /* 5-bits */
{
BbpR49.byte = (BbpR49.byte & 0x1F);
}
/* (p) TssiPlusBoundaryG[0] = 0 = (m) TssiMinusBoundaryG[0] */
/* compensate: +4 +3 +2 +1 0 -1 -2 -3 -4 * steps */
/* step value is defined in pAd->TxAgcStepG for tx power value */
/* [4]+1+[4] p4 p3 p2 p1 o1 m1 m2 m3 m4 */
/* ex: 0x00 0x15 0x25 0x45 0x88 0xA0 0xB5 0xD0 0xF0
above value are examined in mass factory production */
/* [4] [3] [2] [1] [0] [1] [2] [3] [4] */
/* plus (+) is 0x00 ~ 0x45, minus (-) is 0xa0 ~ 0xf0 */
/* if value is between p1 ~ o1 or o1 ~ s1, no need to adjust tx power */
/* if value is 0xa5, tx power will be -= TxAgcStep*(2-1) */
if (BbpR49.byte > pTssiMinusBoundary[1])
{
/* Reading is larger than the reference value */
/* Check for how large we need to decrease the Tx power */
for (idx = 1; idx < 5; idx++)
{
if (BbpR49.byte <= pTssiMinusBoundary[idx]) /* Found the range */
break;
}
/* The index is the step we should decrease, idx = 0 means there is nothing to compensate */
*pTxAgcCompensate = -(TxAgcStep * (idx-1));
DeltaPwr += (*pTxAgcCompensate);
DBGPRINT(RT_DEBUG_TRACE, ("-- Tx Power, BBP R49=%x, TssiRef=%x, TxAgcStep=%x, step = -%d\n",
BbpR49.byte, TssiRef, TxAgcStep, idx-1));
}
else if (BbpR49.byte < pTssiPlusBoundary[1])
{
/* Reading is smaller than the reference value */
/* Check for how large we need to increase the Tx power */
for (idx = 1; idx < 5; idx++)
{
if (BbpR49.byte >= pTssiPlusBoundary[idx]) /* Found the range*/
break;
}
/* The index is the step we should increase, idx = 0 means there is nothing to compensate */
*pTxAgcCompensate = TxAgcStep * (idx-1);
DeltaPwr += (*pTxAgcCompensate);
DBGPRINT(RT_DEBUG_TRACE, ("++ Tx Power, BBP R49=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
BbpR49.byte, TssiRef, TxAgcStep, idx-1));
}
else
{
*pTxAgcCompensate = 0;
DBGPRINT(RT_DEBUG_TRACE, (" Tx Power, BBP R49=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
BbpR49.byte, TssiRef, TxAgcStep, 0));
}
}
}
else
{
if (pAd->CommonCfg.Channel <= 14)
{
bAutoTxAgc = pAd->bAutoTxAgcG;
pTxAgcCompensate = &pAd->TxAgcCompensateG;
}
else
{
bAutoTxAgc = pAd->bAutoTxAgcA;
pTxAgcCompensate = &pAd->TxAgcCompensateA;
}
if (bAutoTxAgc)
DeltaPwr += (*pTxAgcCompensate);
}
*pDeltaPwr = DeltaPwr;
*pAgcCompensate = *pTxAgcCompensate;
DBGPRINT(RT_DEBUG_INFO, ("<--%s\n", __FUNCTION__));
}
int rt28xx_init(
IN PRTMP_ADAPTER pAd,
IN PSTRING pDefaultMac,
IN PSTRING pHostName)
{
UINT index;
UCHAR TmpPhy;
NDIS_STATUS Status;
UINT32 MacCsr0 = 0;
UINT16 ChipId = 0;
// reset Adapter flags
RTMP_CLEAR_FLAGS(pAd);
// Init BssTab & ChannelInfo tabbles for auto channel select.
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
//#ifdef AUTO_CH_SELECT_ENHANCE
AutoChBssTableInit(pAd);
ChannelInfoInit(pAd);
//#endif // AUTO_CH_SELECT_ENHANCE //
}
#endif // CONFIG_AP_SUPPORT //
#ifdef DOT11_N_SUPPORT
// Allocate BA Reordering memory
if (ba_reordering_resource_init(pAd, MAX_REORDERING_MPDU_NUM) != TRUE)
goto err1;
#endif // DOT11_N_SUPPORT //
// Make sure MAC gets ready.
index = 0;
do
{
RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0);
pAd->MACVersion = MacCsr0;
/* The purpose is to identify RT5390H */
RT28xx_EEPROM_READ16(pAd, 0x00, ChipId);
pAd->ChipId = ChipId;
if ((pAd->MACVersion != 0x00) && (pAd->MACVersion != 0xFFFFFFFF))
break;
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
goto err1;
RTMPusecDelay(10);
} while (index++ < 100);
DBGPRINT(RT_DEBUG_TRACE, ("MAC_CSR0 [ Ver:Rev=0x%08x]\n", pAd->MACVersion));
#ifdef RT5390
if (IS_RT5390H(pAd))
DBGPRINT(RT_DEBUG_ERROR, ("The chip belongs to 0x%04x\n", pAd->ChipId));
#endif /* RT5390 */
#ifdef SPECIFIC_BCN_BUF_SUPPORT
pAd->BcnCB.DYN_MAX_MBSSID_NUM = 1;
if (IS_RT5390(pAd) || IS_RT3593(pAd))
{
pAd->BcnCB.bHighShareMemSupport = 1;
pAd->BcnCB.DYN_HW_BEACON_BASE0 = 0x4000;
pAd->BcnCB.DYN_HW_BEACON_MAX_SIZE = 0x2000;
pAd->BcnCB.DYN_HW_BEACON_MAX_COUNT = 16;
#ifdef MBSS_SUPPORT
#ifdef APCLI_SUPPORT
pAd->BcnCB.DYN_MAX_MBSSID_NUM = 8 - MAX_MESH_NUM;
#else
pAd->BcnCB.DYN_MAX_MBSSID_NUM = 16 - MAX_MESH_NUM;
#endif // APCLI_SUPPORT //
#endif // MBSS_SUPPORT //
}
else
{
pAd->BcnCB.bHighShareMemSupport = 0;
pAd->BcnCB.DYN_HW_BEACON_BASE0 = 0x7800;
pAd->BcnCB.DYN_HW_BEACON_MAX_SIZE = 0x1000;
pAd->BcnCB.DYN_HW_BEACON_MAX_COUNT = 8;
#ifdef MBSS_SUPPORT
pAd->BcnCB.DYN_MAX_MBSSID_NUM = (pAd->BcnCB.DYN_HW_BEACON_MAX_COUNT - MAX_MESH_NUM - MAX_APCLI_NUM);
#endif // MBSS_SUPPORT //
}
#endif // SPECIFIC_BCN_BUF_SUPPORT //
#ifdef RTMP_MAC_PCI
#if defined(RT3090) || defined(RT3592) || defined(RT3390) || defined(RT3593) || defined(RT5390)
/*Iverson patch PCIE L1 issue to make sure that driver can be read,write ,BBP and RF register at pcie L.1 level */
if ((IS_RT3090(pAd) || IS_RT3572(pAd) ||
IS_RT3390(pAd) || IS_RT3593(pAd) || IS_RT5390(pAd))&&pAd->infType==RTMP_DEV_INF_PCIE)
{
RTMP_IO_READ32(pAd, AUX_CTRL, &MacCsr0);
MacCsr0 |= 0x402;
RTMP_IO_WRITE32(pAd, AUX_CTRL, MacCsr0);
DBGPRINT(RT_DEBUG_TRACE, ("AUX_CTRL = 0x%x\n", MacCsr0));
}
#endif // RT3090 //
// To fix driver disable/enable hang issue when radio off
RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x2);
#endif // RTMP_MAC_PCI //
// Disable DMA
RT28XXDMADisable(pAd);
// Load 8051 firmware
Status = NICLoadFirmware(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("NICLoadFirmware failed, Status[=0x%08x]\n", Status));
goto err1;
}
NICLoadRateSwitchingParams(pAd);
// Disable interrupts here which is as soon as possible
// This statement should never be true. We might consider to remove it later
#ifdef RTMP_MAC_PCI
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE))
{
RTMP_ASIC_INTERRUPT_DISABLE(pAd);
}
#endif // RTMP_MAC_PCI //
#ifdef RESOURCE_PRE_ALLOC
Status = RTMPInitTxRxRingMemory(pAd);
#else
Status = RTMPAllocTxRxRingMemory(pAd);
#endif // RESOURCE_PRE_ALLOC //
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("RTMPAllocTxRxMemory failed, Status[=0x%08x]\n", Status));
goto err2;
}
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
// initialize MLME
//
Status = RtmpMgmtTaskInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
goto err3;
Status = MlmeInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("MlmeInit failed, Status[=0x%08x]\n", Status));
goto err4;
}
#ifdef RMTP_RBUS_SUPPORT
#ifdef VIDEO_TURBINE_SUPPORT
VideoConfigInit(pAd);
#endif // VIDEO_TURBINE_SUPPORT //
#endif // RMTP_RBUS_SUPPORT //
// Initialize pAd->StaCfg, pAd->ApCfg, pAd->CommonCfg to manufacture default
//
UserCfgInit(pAd);
Status = RtmpNetTaskInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
goto err5;
// COPY_MAC_ADDR(pAd->ApCfg.MBSSID[apidx].Bssid, netif->hwaddr);
// pAd->bForcePrintTX = TRUE;
CfgInitHook(pAd);
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
APInitialize(pAd);
#endif // CONFIG_AP_SUPPORT //
#ifdef BLOCK_NET_IF
initblockQueueTab(pAd);
#endif // BLOCK_NET_IF //
Status = MeasureReqTabInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("MeasureReqTabInit failed, Status[=0x%08x]\n",Status));
goto err6;
}
Status = TpcReqTabInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("TpcReqTabInit failed, Status[=0x%08x]\n",Status));
goto err6;
}
//
// Init the hardware, we need to init asic before read registry, otherwise mac register will be reset
//
Status = NICInitializeAdapter(pAd, TRUE);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("NICInitializeAdapter failed, Status[=0x%08x]\n", Status));
if (Status != NDIS_STATUS_SUCCESS)
goto err6;
}
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
}
#endif // CONFIG_AP_SUPPORT //
// Read parameters from Config File
/* unknown, it will be updated in NICReadEEPROMParameters */
pAd->RfIcType = RFIC_UNKNOWN;
Status = RTMPReadParametersHook(pAd);
DBGPRINT(RT_DEBUG_OFF, ("1. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("RTMPReadParametersHook failed, Status[=0x%08x]\n",Status));
goto err6;
}
#ifdef DOT11_N_SUPPORT
//Init Ba Capability parameters.
// RT28XX_BA_INIT(pAd);
pAd->CommonCfg.DesiredHtPhy.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity;
pAd->CommonCfg.DesiredHtPhy.AmsduEnable = (USHORT)pAd->CommonCfg.BACapability.field.AmsduEnable;
pAd->CommonCfg.DesiredHtPhy.AmsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize;
pAd->CommonCfg.DesiredHtPhy.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode;
// UPdata to HT IE
pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode;
pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize;
pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity;
#endif // DOT11_N_SUPPORT //
// after reading Registry, we now know if in AP mode or STA mode
// Load 8051 firmware; crash when FW image not existent
// Status = NICLoadFirmware(pAd);
// if (Status != NDIS_STATUS_SUCCESS)
// break;
DBGPRINT(RT_DEBUG_OFF, ("2. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
// We should read EEPROM for all cases. rt2860b
NICReadEEPROMParameters(pAd, (PUCHAR)pDefaultMac);
DBGPRINT(RT_DEBUG_OFF, ("3. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
NICInitAsicFromEEPROM(pAd); //rt2860b
#ifdef RTMP_INTERNAL_TX_ALC
//
// Initialize the desired TSSI table
//
InitDesiredTSSITable(pAd);
#endif // RTMP_INTERNAL_TX_ALC //
#if defined(RT5390) || defined(RT5370)
//
// Temperature compensation, initialize the lookup table
//
DBGPRINT(RT_DEBUG_ERROR, ("IS_RT5392 = %d, bAutoTxAgcG = %d\n", IS_RT5392(pAd), pAd->bAutoTxAgcG));
if (IS_RT5392(pAd) && pAd->bAutoTxAgcG && pAd->CommonCfg.TempComp != 0)
{
InitLookupTable(pAd);
}
#endif // defined(RT5390) || defined(RT5370) //
// Set PHY to appropriate mode
TmpPhy = pAd->CommonCfg.PhyMode;
pAd->CommonCfg.PhyMode = 0xff;
RTMPSetPhyMode(pAd, TmpPhy);
#ifdef DOT11_N_SUPPORT
SetCommonHT(pAd);
#endif // DOT11_N_SUPPORT //
// No valid channels.
if (pAd->ChannelListNum == 0)
{
DBGPRINT(RT_DEBUG_ERROR, ("Wrong configuration. No valid channel found. Check \"ContryCode\" and \"ChannelGeography\" setting.\n"));
goto err6;
}
#ifdef DOT11_N_SUPPORT
DBGPRINT(RT_DEBUG_OFF, ("MCS Set = %02x %02x %02x %02x %02x\n", pAd->CommonCfg.HtCapability.MCSSet[0],
pAd->CommonCfg.HtCapability.MCSSet[1], pAd->CommonCfg.HtCapability.MCSSet[2],
pAd->CommonCfg.HtCapability.MCSSet[3], pAd->CommonCfg.HtCapability.MCSSet[4]));
#endif // DOT11_N_SUPPORT //
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef AP_QLOAD_SUPPORT
/* init QBSS Element */
QBSS_LoadInit(pAd);
#endif // AP_QLOAD_SUPPORT //
//#ifdef DOT11K_RRM_SUPPORT
// RRM_CfgInit(pAd);
//#endif // DOT11K_RRM_SUPPORT //
}
#endif // CONFIG_AP_SUPPORT //
// APInitialize(pAd);
#ifdef IKANOS_VX_1X0
VR_IKANOS_FP_Init(pAd->ApCfg.BssidNum, pAd->PermanentAddress);
#endif // IKANOS_VX_1X0 //
#ifdef CONFIG_AP_SUPPORT
//
// Initialize RF register to default value
//
if (pAd->OpMode == OPMODE_AP)
{
AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
AsicLockChannel(pAd, pAd->CommonCfg.Channel);
}
#endif // CONFIG_AP_SUPPORT //
/*
Some modules init must be called before APStartUp().
Or APStartUp() will make up beacon content and call
other modules API to get some information to fill.
*/
#ifdef WMM_ACM_SUPPORT
#ifdef CONFIG_AP_SUPPORT
ACMP_Init(pAd,
pAd->CommonCfg.APEdcaParm.bACM[0],
pAd->CommonCfg.APEdcaParm.bACM[1],
pAd->CommonCfg.APEdcaParm.bACM[2],
pAd->CommonCfg.APEdcaParm.bACM[3], 0);
#endif // CONFIG_AP_SUPPORT //
#endif // WMM_ACM_SUPPORT //
if (pAd && (Status != NDIS_STATUS_SUCCESS))
{
//
// Undo everything if it failed
//
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE))
{
// NdisMDeregisterInterrupt(&pAd->Interrupt);
RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
}
// RTMPFreeAdapter(pAd); // we will free it in disconnect()
}
else if (pAd)
{
// Microsoft HCT require driver send a disconnect event after driver initialization.
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED);
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE);
DBGPRINT(RT_DEBUG_TRACE, ("NDIS_STATUS_MEDIA_DISCONNECT Event B!\n"));
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
if (pAd->ApCfg.bAutoChannelAtBootup || (pAd->CommonCfg.Channel == 0))
{
UINT8 BBPValue = 0;
// Enable Interrupt first due to we need to scan channel to receive beacons.
RTMP_IRQ_ENABLE(pAd);
// Now Enable RxTx
RTMPEnableRxTx(pAd);
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP);
// Let BBP register at 20MHz to do scan
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
BBPValue &= (~0x18);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
DBGPRINT(RT_DEBUG_ERROR, ("SYNC - BBP R4 to 20MHz.l\n"));
// Now we can receive the beacon and do the listen beacon
// use default BW to select channel
pAd->CommonCfg.Channel = AP_AUTO_CH_SEL(pAd, pAd->ApCfg.AutoChannelAlg);
pAd->ApCfg.bAutoChannelAtBootup = FALSE;
}
#ifdef DOT11_N_SUPPORT
// If phymode > PHY_11ABGN_MIXED and BW=40 check extension channel, after select channel
N_ChannelCheck(pAd);
#ifdef DOT11N_DRAFT3
/*
We only do this Overlapping BSS Scan when system up, for the
other situation of channel changing, we depends on station's
report to adjust ourself.
*/
if (pAd->CommonCfg.bForty_Mhz_Intolerant == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("Disable 20/40 BSSCoex Channel Scan(BssCoex=%d, 40MHzIntolerant=%d)\n",
pAd->CommonCfg.bBssCoexEnable,
pAd->CommonCfg.bForty_Mhz_Intolerant));
}
else if(pAd->CommonCfg.bBssCoexEnable == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("Enable 20/40 BSSCoex Channel Scan(BssCoex=%d)\n",
pAd->CommonCfg.bBssCoexEnable));
APOverlappingBSSScan(pAd);
}
RTMP_11N_D3_TimerInit(pAd);
// RTMPInitTimer(pAd, &pAd->CommonCfg.Bss2040CoexistTimer, GET_TIMER_FUNCTION(Bss2040CoexistTimeOut), pAd, FALSE);
#endif // DOT11N_DRAFT3 //
#endif // DOT11_N_SUPPORT //
#ifdef RT3090
#ifdef TONE_RADAR_DETECT_SUPPORT
if (IS_RT3090A(pAd) || IS_RT3390(pAd) || IS_RT5390(pAd))
pAd->CommonCfg.carrier_func=TONE_RADAR_V2;
else
pAd->CommonCfg.carrier_func=TONE_RADAR_V1;
#endif // TONE_RADAR_DETECT_SUPPORT //
#endif // RT3090 //
APStartUp(pAd);
DBGPRINT(RT_DEBUG_OFF, ("Main bssid = %02x:%02x:%02x:%02x:%02x:%02x\n",
PRINT_MAC(pAd->ApCfg.MBSSID[BSS0].Bssid)));
}
#endif // CONFIG_AP_SUPPORT //
}// end of else
#ifdef WSC_INCLUDED
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
INT apidx;
#ifdef HOSTAPD_SUPPORT
if (pAd->ApCfg.Hostapd == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("WPS is control by hostapd now.\n"));
}
else
#endif //HOSTAPD_SUPPORT//
for (apidx = 0; apidx < pAd->ApCfg.BssidNum; apidx++)
{
PWSC_CTRL pWscControl;
UCHAR zeros16[16]= {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
pWscControl = &pAd->ApCfg.MBSSID[apidx].WscControl;
DBGPRINT(RT_DEBUG_TRACE, ("Generate UUID for apidx(%d)\n", apidx));
if (NdisEqualMemory(&pWscControl->Wsc_Uuid_E[0], zeros16, UUID_LEN_HEX))
WscGenerateUUID(pAd, &pWscControl->Wsc_Uuid_E[0], &pWscControl->Wsc_Uuid_Str[0], apidx, FALSE);
WscInit(pAd, FALSE, apidx);
}
}
#endif // CONFIG_AP_SUPPORT //
/* WSC hardware push button function 0811 */
WSC_HDR_BTN_Init(pAd);
#endif // WSC_INCLUDED //
// Set up the Mac address
RtmpOSNetDevAddrSet(pAd->net_dev, &pAd->CurrentAddress[0]);
// Various AP function init
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef MBSS_SUPPORT
/* the function can not be moved to RT2860_probe() even register_netdev()
is changed as register_netdevice().
Or in some PC, kernel will panic (Fedora 4) */
RT28xx_MBSS_Init(pAd, pAd->net_dev);
#endif // MBSS_SUPPORT //
#ifdef WDS_SUPPORT
RT28xx_WDS_Init(pAd, pAd->net_dev);
#endif // WDS_SUPPORT //
#ifdef APCLI_SUPPORT
RT28xx_ApCli_Init(pAd, pAd->net_dev);
#endif // APCLI_SUPPORT //
}
#endif // CONFIG_AP_SUPPORT //
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef MAT_SUPPORT
MATEngineInit(pAd);
#endif // MAT_SUPPORT //
#ifdef CLIENT_WDS
CliWds_ProxyTabInit(pAd);
#endif // CLIENT_WDS //
}
#endif // CONFIG_AP_SUPPORT //
#ifdef RT33xx
if (IS_RT3390(pAd))
{
RTMP_TxEvmCalibration(pAd);
}
#endif // RT33xx //
DBGPRINT_S(Status, ("<==== rt28xx_init, Status=%x\n", Status));
return TRUE;
err6:
MeasureReqTabExit(pAd);
TpcReqTabExit(pAd);
err5:
RtmpNetTaskExit(pAd);
UserCfgExit(pAd);
err4:
MlmeHalt(pAd);
err3:
RtmpMgmtTaskExit(pAd);
err2:
#ifdef RESOURCE_PRE_ALLOC
RTMPResetTxRxRingMemory(pAd);
#else
RTMPFreeTxRxRingMemory(pAd);
#endif // RESOURCE_PRE_ALLOC //
err1:
#ifdef DOT11_N_SUPPORT
if(pAd->mpdu_blk_pool.mem)
os_free_mem(pAd, pAd->mpdu_blk_pool.mem); // free BA pool
#endif // DOT11_N_SUPPORT //
// shall not set priv to NULL here because the priv didn't been free yet.
//net_dev->priv = 0;
#ifdef INF_AMAZON_SE
err0:
#endif // INF_AMAZON_SE //
#ifdef ST
err0:
#endif // ST //
DBGPRINT(RT_DEBUG_ERROR, ("!!! rt28xx Initialized fail !!!\n"));
return FALSE;
}