void bl(int i)
{
/*
I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S);
imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
if ConditionPassed() then
EncodingSpecificOperations();
next_instr_addr = PC;
LR = next_instr_addr<31:1> : '1';
SelectInstrSet(InstrSet_Thumb);
BranchWritePC(PC + imm32);
*/
int i1,i2,imm32,next_instr_addr;
*((int *)(&branchWithLink)) = i;
i1=!(branchWithLink.j1^branchWithLink.s);
i2=!(branchWithLink.j2^branchWithLink.s);
imm32=(branchWithLink.s<<24)|(i1<<23)|(i2<<22)|(branchWithLink.off2<<12)|(branchWithLink.off1<<1);
imm32 &= 0xFFFFFFFE;
//SignExtend
if(imm32 & 0x01000000)
imm32 |= 0xFE000000;
else
imm32 &= 0x01FFFFFF;
if(InITBlock() && !LastInITBlock())
printf("UNPREDICTABLE instruction.\n");
else{
EncodingSpecificOperations();
next_instr_addr=get_pc();
set_lr(next_instr_addr | 0x00000001);
//SelectInstrSet(InstrSet_Thumb); questionhi
BranchWritePC(get_pc()+imm32);
}
}
void b_t4(int i)
{
/*
I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S);
imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
if ConditionPassed() then
EncodingSpecificOperations();
BranchWritePC(PC + imm32);
*/
int imm32,i1,i2;
*((int *)(&branch)) = i;
i1=!(branch.j1^branch.s);
i2=!(branch.j2^branch.s);
imm32=(branch.s<<24)|(i1<<23)+(i2<<22)|(branch.off2<<12)|(branch.off1<<1);
imm32 &= 0xFFFFFFFE;
//SignExtend
if(imm32 & 0x01000000)
imm32 |= 0xFE000000;
else
imm32 &= 0x01FFFFFF;
if(InITBlock() && !LastInITBlock())
printf("UNPREDICTABLE instruction.\n");
else{
EncodingSpecificOperations();
BranchWritePC(get_pc()+imm32);
}
}
int preprocess_B(Instruction *out, Emulator *emul)
{
SignExtend_plgtab(&out->imm);
if(InITBlock(emul->it_state))
{
process_state(&emul->it_state, out->name_in, emul->dic->states_tab);
out->it_flag = IN;
}
return 0;
}
int preprocess_pop_push(Instruction *out, Emulator *emul)
{
if(out->encoding != 3)
preprocess_reglist(out);
if(InITBlock(emul->it_state))
{
process_state(&emul->it_state, out->name_in, emul->dic->states_tab);
out->it_flag = IN;
}
return 0;
}
int preprocess_ldr(Instruction *out, Emulator *emul)
{
ZeroExtend_plgtab(&out->imm);
if(InITBlock(emul->it_state))
{
process_state(&emul->it_state, out->name_in, emul->dic->states_tab);
out->it_flag = IN;
}
if(out->encoding == 1 || out->encoding == 2)
out->imm.plages->value <<= 2;
return 0;
}
int preprocess_sub_sp(Instruction *out, Emulator *emul)
{
ZeroExtend_plgtab(&out->imm);
if(InITBlock(emul->it_state))
{
process_state(&emul->it_state, out->name_in, emul->dic->states_tab);
out->it_flag = IN;
}
if(out->encoding == 1)
out->imm.plages->value <<= 2; // décalage de 2 bits, cf spécifications
return 0;
}
void tbh(int i){
int n,m,halfwords;
*((int *)(&TbH)) = i;
n = TbH.rn;
m = TbH.rm;
if(n == 13 || Bad_Reg(m))
printf(" It is unpredictable!");
else if(InITBlock() && !LastInITBlock())
printf(" It is unpredictable!");
else{
halfwords = get_MemU(get_general_register(n) + lsl(get_general_register(m),1),1);
halfwords = halfwords << 1;
BranchWritePC(get_pc() + halfwords);
//printf(" *****tbh");
}
}
int preprocess_BL(Instruction *out, Emulator *emul)
{
// Ji = not(S xor Ii)
out->imm.plages[1].value = (~ (out->imm.plages[0].value ^ out->imm.plages[1].value) ) & 1;
out->imm.plages[2].value = (~ (out->imm.plages[0].value ^ out->imm.plages[2].value) ) & 1;
SignExtend_plgtab(&out->imm);
if(InITBlock(emul->it_state))
{
process_state(&emul->it_state, out->name_in, emul->dic->states_tab);
out->it_flag = IN;
}
return 0;
}
void b_t3(int i)
{
/*
imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32);
if cond<3:1> == '111' then
SEE Branches, miscellaneous control instructions on page A4-30;
if InITBlock() then UNPREDICTABLE;
if ConditionPassed() then
EncodingSpecificOperations();
BranchWritePC(PC + imm32);
*/
int imm32;
*((int*)(&conditionalBranch))=i;
imm32=(conditionalBranch.s<<20)|(conditionalBranch.j2<<19)|(conditionalBranch.j1<<18)|
(conditionalBranch.off2<<12)|(conditionalBranch.off1<<1);
imm32 &= 0xFFFFFFFE;
//SignExtend
if(imm32 & 0x00100000)
imm32 |= 0xFFE00000;
else
imm32 &= 0x001FFFFF;
if(conditionalBranch.cond>=14){
//question?
printf("Error!Branch conditonal instruction,con<3:1>=111\n");
return;
}
else if(InITBlock())
printf("UNPREDICTABLE instruction\n");
else if(ConditionPassed(conditionalBranch.cond)){
EncodingSpecificOperations();
BranchWritePC(get_pc()+imm32);
}
}
int preprocess_add_reg_16(Instruction *out, Emulator *emul)
{
Plgtab rdntab;
plgtabdup(&rdntab, &out->reg);
rdntab.size = 2; // il ne doit pas prendre en compte la dernière case
ZeroExtend_plgtab(&rdntab); // met la taille à 1 et concatène les valeurs binaires
rdntab.plages = realloc(rdntab.plages, 2 * sizeof(Plage));
if(rdntab.plages == NULL)
return 2;
rdntab.size = 2;
rdntab.plages[1] = out->reg.plages[2];
free(out->reg.plages);
out->reg = rdntab;
if(InITBlock(emul->it_state))
{
process_state(&emul->it_state, out->name_in, emul->dic->states_tab);
out->it_flag = IN;
}
return 0;
}
