/*-------------------------------------------------------------------*/
void Map42_Write( WORD wAddr, BYTE byData )
{
switch ( wAddr & 0xe003 )
{
/* Set ROM Banks */
case 0xe000:
SRAMBANK = ROMPAGE( ( byData & 0x0f ) % ( NesHeader.byRomSize << 1 ) );
break;
case 0xe001:
if ( byData & 0x08 )
{
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
break;
case 0xe002:
if ( byData & 0x02 )
{
Map42_IRQ_Enable = 1;
} else {
Map42_IRQ_Enable = 0;
Map42_IRQ_Cnt = 0;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map70_Write( WORD wAddr, BYTE byData )
{
BYTE byChrBank = byData & 0x0f;
BYTE byPrgBank = ( byData & 0x70 ) >> 4;
/* Set ROM Banks */
byPrgBank <<= 1;
byPrgBank %= ( NesHeader.byRomSize << 1 );
ROMBANK0 = ROMPAGE( byPrgBank );
ROMBANK1 = ROMPAGE( byPrgBank + 1 );
/* Set PPU Banks */
byChrBank <<= 3;
byChrBank %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 0 ] = VROMPAGE( byChrBank + 0 );
PPUBANK[ 1 ] = VROMPAGE( byChrBank + 1 );
PPUBANK[ 2 ] = VROMPAGE( byChrBank + 2 );
PPUBANK[ 3 ] = VROMPAGE( byChrBank + 3 );
PPUBANK[ 4 ] = VROMPAGE( byChrBank + 4 );
PPUBANK[ 5 ] = VROMPAGE( byChrBank + 5 );
PPUBANK[ 6 ] = VROMPAGE( byChrBank + 6 );
PPUBANK[ 7 ] = VROMPAGE( byChrBank + 7 );
InfoNES_SetupChr();
/* Name Table Mirroring */
if ( byData & 0x80 )
{
InfoNES_Mirroring( 2 );
} else {
InfoNES_Mirroring( 3 );
}
}
/*-------------------------------------------------------------------*/
void Map202_WriteSub( WORD wAddr, BYTE byData )
{
int bank = (wAddr>>1) & 0x07;
/* Set ROM Banks */
ROMBANK0 = ROMPAGE(((bank<<1)+0) % (NesHeader.byRomSize<<1));
ROMBANK1 = ROMPAGE(((bank<<1)+1) % (NesHeader.byRomSize<<1));
if ((wAddr&0x0c) == 0x0c) {
ROMBANK2 = ROMPAGE((((bank+1)<<1)+0) % (NesHeader.byRomSize<<1));
ROMBANK3 = ROMPAGE((((bank+1)<<1)+1) % (NesHeader.byRomSize<<1));
} else {
ROMBANK2 = ROMPAGE((((bank+0)<<1)+0) % (NesHeader.byRomSize<<1));
ROMBANK3 = ROMPAGE((((bank+0)<<1)+1) % (NesHeader.byRomSize<<1));
}
/* Set PPU Banks */
PPUBANK[0] = VROMPAGE(((bank<<3)+0) % (NesHeader.byVRomSize<<3));
PPUBANK[1] = VROMPAGE(((bank<<3)+1) % (NesHeader.byVRomSize<<3));
PPUBANK[2] = VROMPAGE(((bank<<3)+2) % (NesHeader.byVRomSize<<3));
PPUBANK[3] = VROMPAGE(((bank<<3)+3) % (NesHeader.byVRomSize<<3));
PPUBANK[4] = VROMPAGE(((bank<<3)+4) % (NesHeader.byVRomSize<<3));
PPUBANK[5] = VROMPAGE(((bank<<3)+5) % (NesHeader.byVRomSize<<3));
PPUBANK[6] = VROMPAGE(((bank<<3)+6) % (NesHeader.byVRomSize<<3));
PPUBANK[7] = VROMPAGE(((bank<<3)+7) % (NesHeader.byVRomSize<<3));
InfoNES_SetupChr();
if ( wAddr & 0x01 ) {
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
}
/*-------------------------------------------------------------------*/
void Map245_Write( WORD wAddr, BYTE byData )
{
switch( wAddr&0xF7FF ) {
case 0x8000:
Map245_Reg[0] = byData;
break;
case 0x8001:
Map245_Reg[1] = byData;
switch( Map245_Reg[0] ) {
case 0x00:
Map245_Reg[3]=(byData & 2 )<<5;
ROMBANK2 = ROMPAGE((0x3E|Map245_Reg[3]) % (NesHeader.byRomSize<<1));
ROMBANK3 = ROMPAGE((0x3F|Map245_Reg[3]) % (NesHeader.byRomSize<<1));
break;
case 0x06:
Map245_Prg0=byData;
break;
case 0x07:
Map245_Prg1=byData;
break;
}
ROMBANK0 = ROMPAGE((Map245_Prg0|Map245_Reg[3]) % (NesHeader.byRomSize<<1));
ROMBANK1 = ROMPAGE((Map245_Prg1|Map245_Reg[3]) % (NesHeader.byRomSize<<1));
break;
case 0xA000:
Map245_Reg[2] = byData;
if( !ROM_FourScr ) {
if( byData & 0x01 ) InfoNES_Mirroring( 0 );
else InfoNES_Mirroring( 1 );
}
break;
case 0xA001:
break;
case 0xC000:
Map245_Reg[4] = byData;
Map245_IRQ_Counter = byData;
Map245_IRQ_Request = 0;
break;
case 0xC001:
Map245_Reg[5] = byData;
Map245_IRQ_Latch = byData;
Map245_IRQ_Request = 0;
break;
case 0xE000:
Map245_Reg[6] = byData;
Map245_IRQ_Enable = 0;
Map245_IRQ_Request = 0;
break;
case 0xE001:
Map245_Reg[7] = byData;
Map245_IRQ_Enable = 1;
Map245_IRQ_Request = 0;
break;
}
}
/*-------------------------------------------------------------------*/
void Map134_Apu( WORD wAddr, BYTE byData )
{
switch( wAddr & 0x4101 ) {
case 0x4100:
Map134_Cmd = byData & 0x07;
break;
case 0x4101:
switch( Map134_Cmd ) {
case 0:
Map134_Prg = 0;
Map134_Chr = 3;
break;
case 4:
Map134_Chr &= 0x3;
Map134_Chr |= (byData & 0x07) << 2;
break;
case 5:
Map134_Prg = byData & 0x07;
break;
case 6:
Map134_Chr &= 0x1C;
Map134_Chr |= byData & 0x3;
break;
case 7:
if( byData & 0x01 ) InfoNES_Mirroring( 0 );
else InfoNES_Mirroring( 1 );
break;
}
break;
}
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( ((Map134_Prg<<2) + 0 ) % (NesHeader.byRomSize << 1) );
ROMBANK1 = ROMPAGE( ((Map134_Prg<<2) + 1 ) % (NesHeader.byRomSize << 1) );
ROMBANK2 = ROMPAGE( ((Map134_Prg<<2) + 2 ) % (NesHeader.byRomSize << 1) );
ROMBANK3 = ROMPAGE( ((Map134_Prg<<2) + 3 ) % (NesHeader.byRomSize << 1) );
/* Set PPU Banks */
PPUBANK[ 0 ] = VROMPAGE( ((Map134_Chr<<3) + 0) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 1 ] = VROMPAGE( ((Map134_Chr<<3) + 1) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 2 ] = VROMPAGE( ((Map134_Chr<<3) + 2) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 3 ] = VROMPAGE( ((Map134_Chr<<3) + 3) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 4 ] = VROMPAGE( ((Map134_Chr<<3) + 4) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 5 ] = VROMPAGE( ((Map134_Chr<<3) + 5) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 6 ] = VROMPAGE( ((Map134_Chr<<3) + 6) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 7 ] = VROMPAGE( ((Map134_Chr<<3) + 7) % (NesHeader.byVRomSize << 3) );
InfoNES_SetupChr();
//Map134_Wram[ wAddr & 0x1fff ] = byData;
}
/*-------------------------------------------------------------------*/
void Map109_Apu( WORD wAddr, BYTE byData )
{
switch( wAddr ) {
case 0x4100:
Map109_Reg = byData;
break;
case 0x4101:
switch( Map109_Reg ) {
case 0:
Map109_Chr0 = byData;
Map109_Set_PPU_Banks();
break;
case 1:
Map109_Chr1 = byData;
Map109_Set_PPU_Banks();
break;
case 2:
Map109_Chr2 = byData;
Map109_Set_PPU_Banks();
break;
case 3:
Map109_Chr3 = byData;
Map109_Set_PPU_Banks();
break;
case 4:
Map109_Chrmode0 = byData & 0x01;
Map109_Set_PPU_Banks();
break;
case 5:
ROMBANK0 = ROMPAGE( ( ( byData & 0x07 ) + 0 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK1 = ROMPAGE( ( ( byData & 0x07 ) + 1 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK2 = ROMPAGE( ( ( byData & 0x07 ) + 2 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK3 = ROMPAGE( ( ( byData & 0x07 ) + 3 ) % ( NesHeader.byRomSize << 1 ) );
break;
case 6:
Map109_Chrmode1 = byData & 0x07;
Map109_Set_PPU_Banks();
break;
case 7:
if( byData & 0x01 ) InfoNES_Mirroring( 0 );
else InfoNES_Mirroring( 1 );
break;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map255_Init()
{
int nPage;
/* Initialize Mapper */
MapperInit = Map255_Init;
/* Write to Mapper */
MapperWrite = Map255_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map255_Apu;
/* Read from APU */
MapperReadApu = Map255_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMPAGE( 2 );
ROMBANK3 = ROMPAGE( 3 );
/* Set PPU Banks */
if ( NesHeader.byVRomSize > 0 ) {
for ( nPage = 0; nPage < 8; ++nPage )
PPUBANK[ nPage ] = VROMPAGE( nPage );
InfoNES_SetupChr();
}
/* Set Registers */
InfoNES_Mirroring( 1 );
Map255_Reg[0] = 0;
Map255_Reg[1] = 0;
Map255_Reg[2] = 0;
Map255_Reg[3] = 0;
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
void Map90_Sync_Mirror( void )
{
BYTE byPage;
DWORD dwNamBank[ 4 ];
for ( byPage = 0; byPage < 4; byPage++ )
{
dwNamBank[ byPage ] =
( (DWORD)Map90_Nam_High_Reg[ byPage ] << 8 ) | (DWORD)Map90_Nam_Low_Reg[ byPage ];
}
if ( Map90_Mirror_Mode )
{
for ( byPage = 0; byPage < 4; byPage++ )
{
if ( !Map90_Nam_High_Reg[ byPage ] && ( Map90_Nam_Low_Reg[ byPage ] == byPage ) )
{
Map90_Mirror_Mode = 0;
}
}
if ( Map90_Mirror_Mode )
{
PPUBANK[ NAME_TABLE0 ] = VROMPAGE( dwNamBank[ 0 ] % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ NAME_TABLE1 ] = VROMPAGE( dwNamBank[ 1 ] % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ NAME_TABLE2 ] = VROMPAGE( dwNamBank[ 2 ] % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ NAME_TABLE3 ] = VROMPAGE( dwNamBank[ 3 ] % ( NesHeader.byVRomSize << 3 ) );
}
} else {
switch ( Map90_Mirror_Type )
{
case 0x00:
InfoNES_Mirroring( 1 );
break;
case 0x01:
InfoNES_Mirroring( 0 );
break;
default:
InfoNES_Mirroring( 3 );
break;
}
}
}
/*-------------------------------------------------------------------*/
void Map229_Write( WORD wAddr, BYTE byData )
{
if( wAddr & 0x001E ) {
BYTE byPrg = wAddr&0x001F;
ROMBANK0 = ROMPAGE(((byPrg<<1)+0) % (NesHeader.byRomSize<<1));
ROMBANK1 = ROMPAGE(((byPrg<<1)+1) % (NesHeader.byRomSize<<1));
ROMBANK2 = ROMPAGE(((byPrg<<1)+0) % (NesHeader.byRomSize<<1));
ROMBANK3 = ROMPAGE(((byPrg<<1)+1) % (NesHeader.byRomSize<<1));
BYTE byChr = wAddr & 0x0FFF;
PPUBANK[ 0 ] = VROMPAGE(((byChr<<3) + 0) % (NesHeader.byVRomSize<<3));
PPUBANK[ 1 ] = VROMPAGE(((byChr<<3) + 1) % (NesHeader.byVRomSize<<3));
PPUBANK[ 2 ] = VROMPAGE(((byChr<<3) + 2) % (NesHeader.byVRomSize<<3));
PPUBANK[ 3 ] = VROMPAGE(((byChr<<3) + 3) % (NesHeader.byVRomSize<<3));
PPUBANK[ 4 ] = VROMPAGE(((byChr<<3) + 4) % (NesHeader.byVRomSize<<3));
PPUBANK[ 5 ] = VROMPAGE(((byChr<<3) + 5) % (NesHeader.byVRomSize<<3));
PPUBANK[ 6 ] = VROMPAGE(((byChr<<3) + 6) % (NesHeader.byVRomSize<<3));
PPUBANK[ 7 ] = VROMPAGE(((byChr<<3) + 7) % (NesHeader.byVRomSize<<3));
InfoNES_SetupChr();
} else {
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMPAGE( 2 );
ROMBANK3 = ROMPAGE( 3 );
PPUBANK[ 0 ] = VROMPAGE( 0 );
PPUBANK[ 1 ] = VROMPAGE( 1 );
PPUBANK[ 2 ] = VROMPAGE( 2 );
PPUBANK[ 3 ] = VROMPAGE( 3 );
PPUBANK[ 4 ] = VROMPAGE( 4 );
PPUBANK[ 5 ] = VROMPAGE( 5 );
PPUBANK[ 6 ] = VROMPAGE( 6 );
PPUBANK[ 7 ] = VROMPAGE( 7 );
InfoNES_SetupChr();
}
if( wAddr & 0x0020 ) {
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
}
/*-------------------------------------------------------------------*/
void Map97_Write( WORD wAddr, BYTE byData )
{
/* Set ROM Banks */
if ( wAddr < 0xc000 )
{
BYTE byPrgBank = byData & 0x0f;
byPrgBank <<= 1;
byPrgBank %= ( NesHeader.byRomSize << 1 );
ROMBANK2 = ROMPAGE( byPrgBank );
ROMBANK3 = ROMPAGE( byPrgBank + 1 );
if ( ( byData & 0x80 ) == 0 )
{
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
}
}
/*-------------------------------------------------------------------*/
void Map251_Init()
{
/* Initialize Mapper */
MapperInit = Map251_Init;
/* Write to Mapper */
MapperWrite = Map251_Write;
/* Write to SRAM */
MapperSram = Map251_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMLASTPAGE( 1 );
ROMBANK3 = ROMLASTPAGE( 0 );
/* Set Registers */
InfoNES_Mirroring( 1 );
int i;
for( i = 0; i < 11; i++ )
Map251_Reg[i] = 0;
for( i = 0; i < 4; i++ )
Map251_Breg[i] = 0;
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
void Map71_Write( WORD wAddr, BYTE byData )
{
switch ( wAddr & 0xf000 )
{
case 0x9000:
if ( byData & 0x10 )
{
InfoNES_Mirroring( 2 );
} else {
InfoNES_Mirroring( 3 );
}
break;
/* Set ROM Banks */
case 0xc000:
case 0xd000:
case 0xe000:
case 0xf000:
ROMBANK0 = ROMPAGE( ( ( byData << 1 ) + 0 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK1 = ROMPAGE( ( ( byData << 1 ) + 1 ) % ( NesHeader.byRomSize << 1 ) );
break;
}
}
/*-------------------------------------------------------------------*/
void Map6_Apu( WORD wAddr, BYTE byData )
{
switch ( wAddr )
{
/* Name Table Mirroring */
case 0x42fe:
if ( byData & 0x10 )
{
InfoNES_Mirroring( 2 );
} else {
InfoNES_Mirroring( 3 );
}
break;
case 0x42ff:
if ( byData & 0x10 )
{
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
break;
case 0x4501:
Map6_IRQ_Enable = 0;
break;
case 0x4502:
Map6_IRQ_Cnt = ( Map6_IRQ_Cnt & 0xff00 ) | (DWORD)byData;
break;
case 0x4503:
Map6_IRQ_Cnt = ( Map6_IRQ_Cnt & 0x00ff ) | ( (DWORD)byData << 8 );
Map6_IRQ_Enable = 1;
break;
}
}
/*-------------------------------------------------------------------*/
void Map230_Write( WORD wAddr, BYTE byData )
{
if( Map230_RomSw ) {
ROMBANK0 = ROMPAGE((((byData&0x07)<<1)+0) % (NesHeader.byRomSize<<1));
ROMBANK1 = ROMPAGE((((byData&0x07)<<1)+1) % (NesHeader.byRomSize<<1));
} else {
if( byData & 0x20 ) {
ROMBANK0 = ROMPAGE((((byData&0x1F)<<1)+16) % (NesHeader.byRomSize<<1));
ROMBANK1 = ROMPAGE((((byData&0x1F)<<1)+17) % (NesHeader.byRomSize<<1));
ROMBANK2 = ROMPAGE((((byData&0x1F)<<1)+16) % (NesHeader.byRomSize<<1));
ROMBANK3 = ROMPAGE((((byData&0x1F)<<1)+17) % (NesHeader.byRomSize<<1));
} else {
ROMBANK0 = ROMPAGE((((byData&0x1E)<<1)+16) % (NesHeader.byRomSize<<1));
ROMBANK1 = ROMPAGE((((byData&0x1E)<<1)+17) % (NesHeader.byRomSize<<1));
ROMBANK2 = ROMPAGE((((byData&0x1E)<<1)+18) % (NesHeader.byRomSize<<1));
ROMBANK3 = ROMPAGE((((byData&0x1E)<<1)+19) % (NesHeader.byRomSize<<1));
}
if( byData & 0x40 ) {
InfoNES_Mirroring( 1 );
} else {
InfoNES_Mirroring( 0 );
}
}
}
/*-------------------------------------------------------------------*/
void Map7_Write( WORD wAddr, BYTE byData )
{
BYTE byBank;
/* Set ROM Banks */
byBank = ( byData & 0x07 ) << 2;
byBank %= ( NesHeader.byRomSize << 1 );
ROMBANK0 = ROMPAGE( byBank );
ROMBANK1 = ROMPAGE( byBank + 1 );
ROMBANK2 = ROMPAGE( byBank + 2 );
ROMBANK3 = ROMPAGE( byBank + 3 );
/* Name Table Mirroring */
InfoNES_Mirroring( byData & 0x10 ? 2 : 3 );
}
/*-------------------------------------------------------------------*/
void Map46_Init()
{
/* Initialize Mapper */
MapperInit = Map46_Init;
/* Write to Mapper */
MapperWrite = Map46_Write;
/* Write to SRAM */
MapperSram = Map46_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
Map46_Regs[ 0 ] = Map46_Regs[ 1 ] = Map46_Regs[ 2 ] = Map46_Regs[ 3 ] = 0;
Map46_Set_ROM_Banks();
/* Name Table Mirroring */
InfoNES_Mirroring( 1 );
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
void Map68_SyncMirror( void )
{
if ( Map68_Regs[ 0 ] )
{
switch( Map68_Regs[ 1 ] )
{
case 0x00:
PPUBANK[ 8 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
PPUBANK[ 9 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
PPUBANK[ 10 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
PPUBANK[ 11 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
break;
case 0x01:
PPUBANK[ 8 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
PPUBANK[ 9 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
PPUBANK[ 10 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
PPUBANK[ 11 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
break;
case 0x02:
PPUBANK[ 8 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
PPUBANK[ 9 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
PPUBANK[ 10 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
PPUBANK[ 11 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
break;
case 0x03:
PPUBANK[ 8 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
PPUBANK[ 9 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
PPUBANK[ 10 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
PPUBANK[ 11 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
break;
}
InfoNES_SetupChr();
}
else
{
InfoNES_Mirroring( Map68_Regs[ 1 ] );
}
}
/*-------------------------------------------------------------------*/
void Map32_Write( WORD wAddr, BYTE byData )
{
switch ( wAddr & 0xf000 )
{
case 0x8000:
/* Set ROM Banks */
byData %= ( NesHeader.byRomSize << 1 );
if ( Map32_Saved & 0x02 )
{
ROMBANK2 = ROMPAGE( byData );
} else {
ROMBANK0 = ROMPAGE( byData );
}
break;
case 0x9000:
Map32_Saved = byData;
// Name Table Mirroring
InfoNES_Mirroring( byData & 0x01 );
break;
case 0xa000:
/* Set ROM Banks */
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK1 = ROMPAGE( byData );
break;
case 0xb000:
/* Set PPU Banks */
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ wAddr & 0x0007 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
default:
break;
}
}
/*-------------------------------------------------------------------*/
void Map23_Write( WORD wAddr, BYTE byData )
{
int bank;
switch ( wAddr )
{
case 0x8000:
case 0x8004:
case 0x8008:
case 0x800c:
byData %= ( NesHeader.byRomSize << 1 );
if ( Map23_Regs[ 8 ] )
{
ROMBANK2 = ROMPAGE( byData );
} else {
ROMBANK0 = ROMPAGE( byData );
}
break;
case 0x9000:
switch ( byData & 0x03 )
{
case 0x00:
InfoNES_Mirroring( 1 );
break;
case 0x01:
InfoNES_Mirroring( 0 );
break;
case 0x02:
InfoNES_Mirroring( 3 );
break;
case 0x03:
InfoNES_Mirroring( 2 );
break;
}
break;
case 0x9008:
Map23_Regs[ 8 ] = byData & 0x02;
break;
case 0xa000:
case 0xa004:
case 0xa008:
case 0xa00c:
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK1 = ROMPAGE( byData );
break;
case 0xB000:
case 0xB002:
case 0xB008:
case 0xC000:
case 0xC002:
case 0xC008:
case 0xD000:
case 0xD002:
case 0xD008:
case 0xE000:
case 0xE002:
case 0xE008:
bank=((wAddr>>12)-0xB)*2+((wAddr&2)>>1)+((wAddr&8)>>3);
Map23_Regs[ bank ] = ( Map23_Regs[ bank ] & 0xf0 ) | ( byData & 0x0f );
PPUBANK[ bank ] = VROMPAGE( Map23_Regs[ bank ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xB001:
case 0xB004:
case 0xB003:
case 0xB00C:
case 0xC001:
case 0xC004:
case 0xC003:
case 0xC00C:
case 0xD001:
case 0xD004:
case 0xD003:
case 0xD00C:
case 0xE001:
case 0xE004:
case 0xE003:
case 0xE00C:
bank=((wAddr>>12)-0xB)*2+((wAddr&2)>>1)+((wAddr&8)>>3);
Map23_Regs[ bank ] = ( Map23_Regs[ bank ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
PPUBANK[ bank ] = VROMPAGE( Map23_Regs[ bank ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xf000:
Map23_IRQ_Latch = ( Map23_IRQ_Latch & 0xf0 ) | ( byData & 0x0f );
break;
case 0xf004:
Map23_IRQ_Latch = ( Map23_IRQ_Latch & 0xf0 ) | ( ( byData & 0x0f ) << 4 );
break;
case 0xf008:
Map23_IRQ_Enable = byData & 0x03;
if ( Map23_IRQ_Enable & 0x02 )
{
Map23_IRQ_Cnt = Map23_IRQ_Latch;
}
break;
case 0xf00c:
if ( Map23_IRQ_Enable & 0x01 )
{
Map23_IRQ_Enable |= 0x02;
} else {
Map23_IRQ_Enable &= 0x01;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map17_Apu( WORD wAddr, BYTE byData )
{
switch ( wAddr )
{
case 0x42fe:
if ( ( byData & 0x10 ) == 0 )
{
InfoNES_Mirroring( 3 );
} else {
InfoNES_Mirroring( 2 );
}
break;
case 0x42ff:
if ( ( byData & 0x10 ) == 0 )
{
InfoNES_Mirroring( 1 );
} else {
InfoNES_Mirroring( 0 );
}
break;
case 0x4501:
Map17_IRQ_Enable = 0;
break;
case 0x4502:
Map17_IRQ_Latch = ( Map17_IRQ_Latch & 0xff00 ) | byData;
break;
case 0x4503:
Map17_IRQ_Latch = ( Map17_IRQ_Latch & 0x00ff ) | ( (DWORD)byData << 8 );
Map17_IRQ_Cnt = Map17_IRQ_Latch;
Map17_IRQ_Enable = 1;
break;
case 0x4504:
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK0 = ROMPAGE( byData );
break;
case 0x4505:
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK1 = ROMPAGE( byData );
break;
case 0x4506:
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK2 = ROMPAGE( byData );
break;
case 0x4507:
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK3 = ROMPAGE( byData );
break;
case 0x4510:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 0 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0x4511:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 1 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0x4512:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 2 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0x4513:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 3 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0x4514:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 4 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0x4515:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 5 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0x4516:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 6 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0x4517:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 7 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
}
}
/*-------------------------------------------------------------------*/
void Map24_Write( WORD wAddr, BYTE byData )
{
switch ( wAddr )
{
case 0x8000:
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( ( byData + 0 ) % ( NesHeader.byRomSize << 1) );
ROMBANK1 = ROMPAGE( ( byData + 1 ) % ( NesHeader.byRomSize << 1) );
break;
case 0xb003:
/* Name Table Mirroring */
switch ( byData & 0x0c )
{
case 0x00:
InfoNES_Mirroring( 1 ); /* Vertical */
break;
case 0x04:
InfoNES_Mirroring( 0 ); /* Horizontal */
break;
case 0x08:
InfoNES_Mirroring( 3 ); /* One Screen 0x2000 */
break;
case 0x0c:
InfoNES_Mirroring( 2 ); /* One Screen 0x2400 */
break;
}
break;
case 0xC000:
ROMBANK2 = ROMPAGE( byData % ( NesHeader.byRomSize << 1) );
break;
case 0xD000:
PPUBANK[ 0 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xD001:
PPUBANK[ 1 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xD002:
PPUBANK[ 2 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xD003:
PPUBANK[ 3 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xE000:
PPUBANK[ 4 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xE001:
PPUBANK[ 5 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xE002:
PPUBANK[ 6 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xE003:
PPUBANK[ 7 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xF000:
Map24_IRQ_Latch = byData;
break;
case 0xF001:
Map24_IRQ_State = byData & 0x03;
if(Map24_IRQ_State & 0x02)
{
Map24_IRQ_Count = Map24_IRQ_Latch;
}
break;
case 0xF002:
if(Map24_IRQ_State & 0x01)
{
Map24_IRQ_State |= 0x02;
}
else
{
Map24_IRQ_State &= 0x01;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map115_Write( WORD wAddr, BYTE byData )
{
switch( wAddr & 0xE001 ) {
case 0x8000:
Map115_Reg[0] = byData;
Map115_Set_CPU_Banks();
Map115_Set_PPU_Banks();
break;
case 0x8001:
Map115_Reg[1] = byData;
switch( Map115_Reg[0] & 0x07 ) {
case 0x00:
Map115_Chr0 = byData & 0xFE;
Map115_Chr1 = Map115_Chr0+1;
Map115_Set_PPU_Banks();
break;
case 0x01:
Map115_Chr2 = byData & 0xFE;
Map115_Chr3 = Map115_Chr2+1;
Map115_Set_PPU_Banks();
break;
case 0x02:
Map115_Chr4 = byData;
Map115_Set_PPU_Banks();
break;
case 0x03:
Map115_Chr5 = byData;
Map115_Set_PPU_Banks();
break;
case 0x04:
Map115_Chr6 = byData;
Map115_Set_PPU_Banks();
break;
case 0x05:
Map115_Chr7 = byData;
Map115_Set_PPU_Banks();
break;
case 0x06:
Map115_Prg0 = Map115_Prg0L = byData;
Map115_Set_CPU_Banks();
break;
case 0x07:
Map115_Prg1 = Map115_Prg1L = byData;
Map115_Set_CPU_Banks();
break;
}
break;
case 0xA000:
Map115_Reg[2] = byData;
if ( !ROM_FourScr ) {
if( byData & 0x01 ) InfoNES_Mirroring( 0 );
else InfoNES_Mirroring( 1 );
}
break;
case 0xA001:
Map115_Reg[3] = byData;
break;
case 0xC000:
Map115_Reg[4] = byData;
Map115_IRQ_Counter = byData;
Map115_IRQ_Enable = 0xFF;
break;
case 0xC001:
Map115_Reg[5] = byData;
Map115_IRQ_Latch = byData;
break;
case 0xE000:
Map115_Reg[6] = byData;
Map115_IRQ_Enable = 0;
break;
case 0xE001:
Map115_Reg[7] = byData;
Map115_IRQ_Enable = 0xFF;
break;
}
}
/*-------------------------------------------------------------------*/
void Map48_Write( WORD wAddr, BYTE byData )
{
switch ( wAddr )
{
case 0x8000:
/* Name Table Mirroring */
if ( !Map48_Regs[ 0 ] )
{
if ( byData & 0x40 )
{
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
}
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( byData % ( NesHeader.byRomSize << 1 ) );
break;
case 0x8001:
/* Set ROM Banks */
ROMBANK1 = ROMPAGE( byData % ( NesHeader.byRomSize << 1 ) );
break;
/* Set PPU Banks */
case 0x8002:
PPUBANK[ 0 ] = VROMPAGE( ( ( byData << 1 ) + 0 ) % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ 1 ] = VROMPAGE( ( ( byData << 1 ) + 1 ) % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0x8003:
PPUBANK[ 2 ] = VROMPAGE( ( ( byData << 1 ) + 0 ) % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ 3 ] = VROMPAGE( ( ( byData << 1 ) + 1 ) % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xa000:
PPUBANK[ 4 ] = VROMPAGE( ( ( byData << 1 ) + 0 ) % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xa001:
PPUBANK[ 5 ] = VROMPAGE( ( ( byData << 1 ) + 0 ) % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xa002:
PPUBANK[ 6 ] = VROMPAGE( ( ( byData << 1 ) + 0 ) % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xa003:
PPUBANK[ 7 ] = VROMPAGE( ( ( byData << 1 ) + 0 ) % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xc000:
Map48_IRQ_Cnt = byData;
break;
case 0xc001:
Map48_IRQ_Enable = byData & 0x01;
break;
case 0xe000:
/* Name Table Mirroring */
if ( byData & 0x40 )
{
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
Map48_Regs[ 0 ] = 1;
break;
}
}
/*-------------------------------------------------------------------*/
void Map18_Write( WORD wAddr, BYTE byData )
{
switch( wAddr )
{
/* Set ROM Banks */
case 0x8000:
Map18_Regs[ 0 ] = ( Map18_Regs[ 0 ] & 0xf0 ) | ( byData & 0x0f );
ROMBANK0 = ROMPAGE( Map18_Regs[ 0 ] % ( NesHeader.byRomSize << 1 ) );
break;
case 0x8001:
Map18_Regs[ 0 ] = ( Map18_Regs[ 0 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
ROMBANK0 = ROMPAGE( Map18_Regs[ 0 ] % ( NesHeader.byRomSize << 1 ) );
break;
case 0x8002:
Map18_Regs[ 1 ] = ( Map18_Regs[ 1 ] & 0xf0 ) | ( byData & 0x0f );
ROMBANK1 = ROMPAGE( Map18_Regs[ 1 ] % ( NesHeader.byRomSize << 1 ) );
break;
case 0x8003:
Map18_Regs[ 1 ] = ( Map18_Regs[ 1 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
ROMBANK1 = ROMPAGE( Map18_Regs[ 1 ] % ( NesHeader.byRomSize << 1 ) );
break;
case 0x9000:
Map18_Regs[ 2 ] = ( Map18_Regs[ 2 ] & 0xf0 ) | ( byData & 0x0f );
ROMBANK2 = ROMPAGE( Map18_Regs[ 2 ] % ( NesHeader.byRomSize << 1 ) );
break;
case 0x9001:
Map18_Regs[ 2 ] = ( Map18_Regs[ 2 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
ROMBANK2 = ROMPAGE( Map18_Regs[ 2 ] % ( NesHeader.byRomSize << 1 ) );
break;
/* Set PPU Banks */
case 0xA000:
Map18_Regs[ 3 ] = ( Map18_Regs[ 3 ] & 0xf0 ) | ( byData & 0x0f );
PPUBANK[ 0 ] = VROMPAGE( Map18_Regs[ 3 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xA001:
Map18_Regs[ 3 ] = ( Map18_Regs[ 3 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
PPUBANK[ 0 ] = VROMPAGE( Map18_Regs[ 3 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xA002:
Map18_Regs[ 4 ] = ( Map18_Regs[ 4 ] & 0xf0 ) | ( byData & 0x0f );
PPUBANK[ 1 ] = VROMPAGE( Map18_Regs[ 4 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xA003:
Map18_Regs[ 4 ] = ( Map18_Regs[ 4 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
PPUBANK[ 1 ] = VROMPAGE( Map18_Regs[ 4 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xB000:
Map18_Regs[ 5 ] = ( Map18_Regs[ 5 ] & 0xf0 ) | ( byData & 0x0f );
PPUBANK[ 2 ] = VROMPAGE( Map18_Regs[ 5 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xB001:
Map18_Regs[ 5 ] = ( Map18_Regs[ 5 ] &0x0f ) | ( ( byData & 0x0f ) << 4 );
PPUBANK[ 2 ] = VROMPAGE( Map18_Regs[ 5 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xB002:
Map18_Regs[ 6 ] = ( Map18_Regs[ 6 ] & 0xf0 ) | ( byData & 0x0f );
PPUBANK[ 3 ] = VROMPAGE( Map18_Regs[ 6 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xB003:
Map18_Regs[ 6 ] = ( Map18_Regs[ 6 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
PPUBANK[ 3 ] = VROMPAGE( Map18_Regs[ 6 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xC000:
Map18_Regs[ 7 ] = ( Map18_Regs[ 7 ] & 0xf0 ) | ( byData & 0x0f );
PPUBANK[ 4 ] = VROMPAGE( Map18_Regs[ 7 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xC001:
Map18_Regs[ 7 ] = ( Map18_Regs[ 7 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
PPUBANK[ 4 ] = VROMPAGE( Map18_Regs[ 7 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xC002:
Map18_Regs[ 8 ] = ( Map18_Regs[ 8 ] & 0xf0 ) | ( byData & 0x0f );
PPUBANK[ 5 ] = VROMPAGE( Map18_Regs[ 8 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xC003:
Map18_Regs[ 8 ] = ( Map18_Regs[ 8 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
PPUBANK[ 5 ] = VROMPAGE( Map18_Regs[ 8 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xD000:
Map18_Regs[ 9 ] = ( Map18_Regs[ 9 ] & 0xf0 ) | ( byData & 0x0f );
PPUBANK[ 6 ] = VROMPAGE( Map18_Regs[ 9 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xD001:
Map18_Regs[ 9 ] = ( Map18_Regs[ 9 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
PPUBANK[ 6 ] = VROMPAGE( Map18_Regs[ 9 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xD002:
Map18_Regs[ 10 ] = ( Map18_Regs[ 10 ] & 0xf0 ) | ( byData & 0x0f );
PPUBANK[ 7 ] = VROMPAGE( Map18_Regs[ 10 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xD003:
Map18_Regs[ 10 ] = ( Map18_Regs[ 10 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
PPUBANK[ 7 ] = VROMPAGE( Map18_Regs[ 10 ] % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xE000:
Map18_IRQ_Latch = ( Map18_IRQ_Latch & 0xfff0 ) | ( byData & 0x0f );
break;
case 0xE001:
Map18_IRQ_Latch = ( Map18_IRQ_Latch & 0xff0f ) | ( ( byData & 0x0f ) << 4 );
break;
case 0xE002:
Map18_IRQ_Latch = ( Map18_IRQ_Latch & 0xf0ff ) | ( ( byData & 0x0f ) << 8 );
break;
case 0xE003:
Map18_IRQ_Latch = ( Map18_IRQ_Latch & 0x0fff ) | ( ( byData & 0x0f ) << 12 );
break;
case 0xF000:
if ( ( byData & 0x01 ) == 0 )
{
Map18_IRQ_Cnt = 0;
} else {
Map18_IRQ_Cnt = Map18_IRQ_Latch;
}
break;
case 0xF001:
Map18_IRQ_Enable = byData & 0x01;
break;
/* Name Table Mirroring */
case 0xF002:
switch ( byData & 0x03 )
{
case 0:
InfoNES_Mirroring( 0 ); /* Horizontal */
break;
case 1:
InfoNES_Mirroring( 1 ); /* Vertical */
break;
case 2:
InfoNES_Mirroring( 3 ); /* One Screen 0x2000 */
break;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map248_Write( WORD wAddr, BYTE byData )
{
switch( wAddr & 0xE001 ) {
case 0x8000:
Map248_Reg[0] = byData;
Map248_Set_CPU_Banks();
Map248_Set_PPU_Banks();
break;
case 0x8001:
Map248_Reg[1] = byData;
switch( Map248_Reg[0] & 0x07 ) {
case 0x00:
Map248_Chr01 = byData & 0xFE;
Map248_Set_PPU_Banks();
break;
case 0x01:
Map248_Chr23 = byData & 0xFE;
Map248_Set_PPU_Banks();
break;
case 0x02:
Map248_Chr4 = byData;
Map248_Set_PPU_Banks();
break;
case 0x03:
Map248_Chr5 = byData;
Map248_Set_PPU_Banks();
break;
case 0x04:
Map248_Chr6 = byData;
Map248_Set_PPU_Banks();
break;
case 0x05:
Map248_Chr7 = byData;
Map248_Set_PPU_Banks();
break;
case 0x06:
Map248_Prg0 = byData;
Map248_Set_CPU_Banks();
break;
case 0x07:
Map248_Prg1 = byData;
Map248_Set_CPU_Banks();
break;
}
break;
case 0xA000:
Map248_Reg[2] = byData;
if( !ROM_FourScr ) {
if( byData & 0x01 ) {
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
}
break;
case 0xC000:
Map248_IRQ_Enable=0;
Map248_IRQ_Latch=0xBE;
Map248_IRQ_Counter =0xBE;
break;
case 0xC001:
Map248_IRQ_Enable=1;
Map248_IRQ_Latch=0xBE;
Map248_IRQ_Counter=0xBE;
break;
}
}
/*-------------------------------------------------------------------*/
void Map26_Write( WORD wAddr, BYTE byData )
{
switch ( wAddr )
{
/* Set ROM Banks */
case 0x8000:
byData <<= 1;
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK0 = ROMPAGE( byData + 0 );
ROMBANK1 = ROMPAGE( byData + 1 );
break;
/* Name Table Mirroring */
case 0xb003:
switch ( byData & 0x7f )
{
case 0x08:
case 0x2c:
InfoNES_Mirroring( 2 ); /* One Screen 0x2400 */
break;
case 0x20:
InfoNES_Mirroring( 1 ); /* Vertical */
break;
case 0x24:
InfoNES_Mirroring( 0 ); /* Horizontal */
break;
case 0x28:
InfoNES_Mirroring( 3 ); /* One Screen 0x2000 */
break;
}
break;
/* Set ROM Banks */
case 0xc000:
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK2 = ROMPAGE( byData );
InfoNES_SetupChr();
break;
/* Set PPU Bank */
case 0xd000:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 0 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0xd001:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 2 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0xd002:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 1 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0xd003:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 3 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0xe000:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 4 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0xe001:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 6 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0xe002:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 5 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
case 0xe003:
byData %= ( NesHeader.byVRomSize << 3 );
PPUBANK[ 7 ] = VROMPAGE( byData );
InfoNES_SetupChr();
break;
/* Set IRQ Registers */
case 0xf000:
Map26_IRQ_Latch = byData;
break;
case 0xf001:
Map26_IRQ_Enable = byData & 0x01;
break;
case 0xf002:
Map26_IRQ_Enable = byData & 0x03;
if ( Map26_IRQ_Enable & 0x02 )
{
Map26_IRQ_Cnt = Map26_IRQ_Latch;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map74_Write( WORD wAddr, BYTE byData )
{
DWORD dwBankNum;
switch ( wAddr & 0xe001 )
{
case 0x8000:
Map74_Regs[ 0 ] = byData;
Map74_Set_PPU_Banks();
Map74_Set_CPU_Banks();
break;
case 0x8001:
Map74_Regs[ 1 ] = byData;
dwBankNum = Map74_Regs[ 1 ];
switch ( Map74_Regs[ 0 ] & 0x07 )
{
/* Set PPU Banks */
case 0x00:
if ( NesHeader.byVRomSize > 0 )
{
dwBankNum &= 0xfe;
Map74_Chr01 = dwBankNum;
Map74_Set_PPU_Banks();
}
break;
case 0x01:
if ( NesHeader.byVRomSize > 0 )
{
dwBankNum &= 0xfe;
Map74_Chr23 = dwBankNum;
Map74_Set_PPU_Banks();
}
break;
case 0x02:
if ( NesHeader.byVRomSize > 0 )
{
Map74_Chr4 = dwBankNum;
Map74_Set_PPU_Banks();
}
break;
case 0x03:
if ( NesHeader.byVRomSize > 0 )
{
Map74_Chr5 = dwBankNum;
Map74_Set_PPU_Banks();
}
break;
case 0x04:
if ( NesHeader.byVRomSize > 0 )
{
Map74_Chr6 = dwBankNum;
Map74_Set_PPU_Banks();
}
break;
case 0x05:
if ( NesHeader.byVRomSize > 0 )
{
Map74_Chr7 = dwBankNum;
Map74_Set_PPU_Banks();
}
break;
/* Set ROM Banks */
case 0x06:
Map74_Prg0 = dwBankNum;
Map74_Set_CPU_Banks();
break;
case 0x07:
Map74_Prg1 = dwBankNum;
Map74_Set_CPU_Banks();
break;
}
break;
case 0xa000:
Map74_Regs[ 2 ] = byData;
if ( !ROM_FourScr )
{
if ( byData & 0x01 )
{
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
}
break;
case 0xa001:
Map74_Regs[ 3 ] = byData;
break;
case 0xc000:
Map74_Regs[ 4 ] = byData;
Map74_IRQ_Latch = byData;
break;
case 0xc001:
Map74_Regs[ 5 ] = byData;
if ( PPU_Scanline < 240 )
{
Map74_IRQ_Cnt |= 0x80;
Map74_IRQ_Present = 0xff;
} else {
Map74_IRQ_Cnt |= 0x80;
Map74_IRQ_Present_Vbl = 0xff;
Map74_IRQ_Present = 0;
}
break;
case 0xe000:
Map74_Regs[ 6 ] = byData;
Map74_IRQ_Enable = 0;
Map74_IRQ_Request = 0;
break;
case 0xe001:
Map74_Regs[ 7 ] = byData;
Map74_IRQ_Enable = 1;
Map74_IRQ_Request = 0;
break;
}
}
/*-------------------------------------------------------------------*/
void Map100_Write( WORD wAddr, BYTE byData )
{
switch ( wAddr & 0xE001 )
{
case 0x8000:
Map100_Reg[0] = byData;
break;
case 0x8001:
Map100_Reg[1] = byData;
switch ( Map100_Reg[0] & 0xC7 ) {
case 0x00:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr0 = byData&0xFE;
Map100_Chr1 = Map100_Chr0+1;
Map100_Set_PPU_Banks();
}
break;
case 0x01:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr2 = byData&0xFE;
Map100_Chr3 = Map100_Chr2+1;
Map100_Set_PPU_Banks();
}
break;
case 0x02:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr4 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x03:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr5 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x04:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr6 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x05:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr7 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x06:
Map100_Prg0 = byData;
Map100_Set_CPU_Banks();
break;
case 0x07:
Map100_Prg1 = byData;
Map100_Set_CPU_Banks();
break;
case 0x46:
Map100_Prg2 = byData;
Map100_Set_CPU_Banks();
break;
case 0x47:
Map100_Prg3 = byData;
Map100_Set_CPU_Banks();
break;
case 0x80:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr4 = byData&0xFE;
Map100_Chr5 = Map100_Chr4+1;
Map100_Set_PPU_Banks();
}
break;
case 0x81:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr6 = byData&0xFE;
Map100_Chr7 = Map100_Chr6+1;
Map100_Set_PPU_Banks();
}
break;
case 0x82:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr0 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x83:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr1 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x84:
if ( NesHeader.byVRomSize > 0 ) {
Map100_Chr2 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x85:
if( NesHeader.byVRomSize > 0 ) {
Map100_Chr3 = byData;
Map100_Set_PPU_Banks();
}
break;
}
break;
case 0xA000:
Map100_Reg[2] = byData;
if ( !ROM_FourScr )
{
if( byData & 0x01 ) InfoNES_Mirroring( 0 );
else InfoNES_Mirroring( 1 );
}
break;
case 0xA001:
Map100_Reg[3] = byData;
break;
case 0xC000:
Map100_Reg[4] = byData;
Map100_IRQ_Cnt = byData;
break;
case 0xC001:
Map100_Reg[5] = byData;
Map100_IRQ_Latch = byData;
break;
case 0xE000:
Map100_Reg[6] = byData;
Map100_IRQ_Enable = 0;
break;
case 0xE001:
Map100_Reg[7] = byData;
Map100_IRQ_Enable = 0xFF;
break;
}
}
/*-------------------------------------------------------------------*/
void Map114_Write( WORD wAddr, BYTE byData )
{
DWORD dwBankNum;
switch ( wAddr & 0xe001 )
{
case 0x8000:
Map114_Regs[ 0 ] = byData;
Map114_Set_PPU_Banks();
Map114_Set_CPU_Banks();
break;
case 0x8001:
Map114_Regs[ 1 ] = byData;
dwBankNum = Map114_Regs[ 1 ];
switch ( Map114_Regs[ 0 ] & 0x07 )
{
/* Set PPU Banks */
case 0x00:
if ( NesHeader.byVRomSize > 0 )
{
dwBankNum &= 0xfe;
Map114_Chr01 = dwBankNum;
Map114_Set_PPU_Banks();
}
break;
case 0x01:
if ( NesHeader.byVRomSize > 0 )
{
dwBankNum &= 0xfe;
Map114_Chr23 = dwBankNum;
Map114_Set_PPU_Banks();
}
break;
case 0x02:
if ( NesHeader.byVRomSize > 0 )
{
Map114_Chr4 = dwBankNum;
Map114_Set_PPU_Banks();
}
break;
case 0x03:
if ( NesHeader.byVRomSize > 0 )
{
Map114_Chr5 = dwBankNum;
Map114_Set_PPU_Banks();
}
break;
case 0x04:
if ( NesHeader.byVRomSize > 0 )
{
Map114_Chr6 = dwBankNum;
Map114_Set_PPU_Banks();
}
break;
case 0x05:
if ( NesHeader.byVRomSize > 0 )
{
Map114_Chr7 = dwBankNum;
Map114_Set_PPU_Banks();
}
break;
/* Set ROM Banks */
case 0x06:
Map114_Prg0 = dwBankNum;
Map114_Set_CPU_Banks();
break;
case 0x07:
Map114_Prg1 = dwBankNum;
Map114_Set_CPU_Banks();
break;
}
break;
case 0xa000:
Map114_Regs[ 2 ] = byData;
if ( !ROM_FourScr )
{
if ( byData & 0x01 )
{
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
}
break;
case 0xa001:
Map114_Regs[ 3 ] = byData;
if ( byData & 0x80 )
{
/* Enable Save RAM $6000-$7fff */
} else {
/* Disable Save RAM $6000-$7fff */
}
break;
case 0xc000:
Map114_Regs[ 4 ] = byData;
Map114_IRQ_Cnt = Map114_Regs[ 4 ];
break;
case 0xc001:
Map114_Regs[ 5 ] = byData;
Map114_IRQ_Latch = Map114_Regs[ 5 ];
break;
case 0xe000:
Map114_Regs[ 6 ] = byData;
Map114_IRQ_Enable = 0;
break;
case 0xe001:
Map114_Regs[ 7 ] = byData;
Map114_IRQ_Enable = 1;
break;
}
}
/*-------------------------------------------------------------------*/
void Map75_Write( WORD wAddr, BYTE byData )
{
switch ( wAddr & 0xf000 )
{
/* Set ROM Banks */
case 0x8000:
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK0 = ROMPAGE( byData );
break;
case 0x9000:
/* Set Mirroring */
if ( byData & 0x01 )
{
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
/* Set PPU Banks */
Map75_Regs[ 0 ] = ( Map75_Regs[ 0 ] & 0x0f ) | ( ( byData & 0x02 ) << 3 );
PPUBANK[ 0 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 0 );
PPUBANK[ 1 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 1 );
PPUBANK[ 2 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 2 );
PPUBANK[ 3 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 3 );
Map75_Regs[ 1 ] = ( Map75_Regs[ 1 ] & 0x0f ) | ( ( byData & 0x04 ) << 2 );
PPUBANK[ 4 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 0 );
PPUBANK[ 5 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 1 );
PPUBANK[ 6 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 2 );
PPUBANK[ 7 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 3 );
InfoNES_SetupChr();
break;
/* Set ROM Banks */
case 0xA000:
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK1 = ROMPAGE( byData );
break;
/* Set ROM Banks */
case 0xC000:
byData %= ( NesHeader.byRomSize << 1 );
ROMBANK2 = ROMPAGE( byData );
break;
case 0xE000:
/* Set PPU Banks */
Map75_Regs[ 0 ] = ( Map75_Regs[ 0 ] & 0x10 ) | ( byData & 0x0f );
PPUBANK[ 0 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 0 );
PPUBANK[ 1 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 1 );
PPUBANK[ 2 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 2 );
PPUBANK[ 3 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 3 );
InfoNES_SetupChr();
break;
case 0xF000:
/* Set PPU Banks */
Map75_Regs[ 1 ] = ( Map75_Regs[ 1 ] & 0x10 ) | ( byData & 0x0f );
PPUBANK[ 4 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 0 );
PPUBANK[ 5 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 1 );
PPUBANK[ 6 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 2 );
PPUBANK[ 7 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 3 );
InfoNES_SetupChr();
break;
}
}
