/*********************************
* 主函数
**********************************/
void main()
{
//uchar i;
Init_IO(); //I/O口初始化,
Init_MCU(); //主函数初始化，T0定时器工作在方式1初始化，显示"请稍等，初始化中",GATE=0,
Init_RAM(); //位变量初始化
Init_Para(); //参数初始化,初始化参数，从IIC读取阈值等信息赋予给参量
Init_Buf(); //并口通讯数组初始化
// Select_Mast(); //判断主从机
Init_Time0(); //开启定时器0。定时器0初始化，工作在方式一，定时初值：H:0xDC,L:0x00;中断计数初始化？定时5ms,NumT0=0;
Lcd_Clear(); //LCD清屏
Lcd_Start(); //显示"清华大学/n核能与新能源技术研究院"
EX0=1; //只允许外部0中断，中断0为键盘
IT0=1; //外部中断0
while(1)
{
// BackUp_Display();
Select_Mast(); //判断主从机，写入主从机标志Flag_Mast=1(主机)0(从机)
key_function(); //按键功能，在while循环中不断检测按键标志，按键标志由按键外部中断来更改
if(Flag_Tim0) //8253计数定时结束时，读取探头的计数，刚开始Flag_Tim0=0，仅当Flag8253Counting计数定时标识为1，且计数器中断次数大于设定的中断次数时，Flag_timo才会等于1
{ //Flag_Tim0为计数器结束标志,初始为0,开机打开定时器中断后,定时器5ms中断一次,检查Flag_Tim0一次,为一表示计数器计时结束
Flag_Tim0 = 0; //定时标志清0
Flag_Warn = 0; //报警标志清0
GetAndDisdata(); //从8253的锁存器得到测量计数器结果,存入至buf数组
ShowData(); //显示测量数据
shortdelay(1000); //
Transfer(); //并行传输数据
// bakeup_conv_data();
Init_8253(); //初始化8253
//定时结束时，立刻又开始初始化进行计数
}
if(Flag_Tim0 == 0) //开启8253计数过程中，处理报警中断，报警有中断吗？
{
if(Flag_Warn_Flash == 1) //主机LED指示灯闪烁间隔定时，Flag_Warn_Flash为LED灯闪烁标志
{
Flag_Warn_Flash = 0;
Led_Flash();
}
if((Flag_Warn_Led==1) && (PCOLSIG==0)) //屏幕上红灯闪烁间隔定时,程序中没有找到PCOLSIG=0的程序段
{
Flag_Warn_Led = 0;
RedLed_Flash(); //灯闪烁
}
}
}
}
void main(void)
#endif
{
uint32_t i;
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_TIMER1 | RST_CLK_PCLK_DMA),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_PORTA), ENABLE);
/* Init NVIC */
SCB->AIRCR = 0x05FA0000 | ((uint32_t)0x500);
SCB->VTOR = 0x08000000;
/* Disable all interrupt */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICER[0] = 0xFFFFFFFF;
/* Disable all DMA request */
MDR_DMA->CHNL_REQ_MASK_CLR = 0xFFFFFFFF;
MDR_DMA->CHNL_USEBURST_CLR = 0xFFFFFFFF;
/* Reset PORTB settings */
PORT_DeInit(MDR_PORTB);
/* Reset PORTF settings */
PORT_DeInit(MDR_PORTF);
/* Configure TIMER1 pins: CH1, CH2 */
/* Configure PORTA pins 1, 3 */
PORT_InitStructure.PORT_Pin = PORT_Pin_1;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_ALTER;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_FAST;
PORT_Init(MDR_PORTA, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = PORT_Pin_3;
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_Init(MDR_PORTA, &PORT_InitStructure);
/* Init RAM */
Init_RAM (DstBuf, BufferSize);
/* Reset all TIMER1 settings */
TIMER_DeInit(MDR_TIMER1);
TIMER_BRGInit(MDR_TIMER1,TIMER_HCLKdiv1);
/* TIM1 configuration ------------------------------------------------*/
/* Initializes the TIMERx Counter ------------------------------------*/
sTIM_CntInit.TIMER_Prescaler = 0x10;
sTIM_CntInit.TIMER_Period = 0x200;
sTIM_CntInit.TIMER_CounterMode = TIMER_CntMode_ClkFixedDir;
sTIM_CntInit.TIMER_CounterDirection = TIMER_CntDir_Up;
sTIM_CntInit.TIMER_EventSource = TIMER_EvSrc_None;
sTIM_CntInit.TIMER_FilterSampling = TIMER_FDTS_TIMER_CLK_div_1;
sTIM_CntInit.TIMER_ARR_UpdateMode = TIMER_ARR_Update_Immediately;
sTIM_CntInit.TIMER_ETR_FilterConf = TIMER_Filter_1FF_at_TIMER_CLK;
sTIM_CntInit.TIMER_ETR_Prescaler = TIMER_ETR_Prescaler_None;
sTIM_CntInit.TIMER_ETR_Polarity = TIMER_ETRPolarity_NonInverted;
sTIM_CntInit.TIMER_BRK_Polarity = TIMER_BRKPolarity_NonInverted;
TIMER_CntInit (MDR_TIMER1,&sTIM_CntInit);
/* Initializes the TIMER1 Channel1 -------------------------------------*/
TIMER_ChnStructInit(&sTIM_ChnInit);
sTIM_ChnInit.TIMER_CH_Number = TIMER_CHANNEL1;
sTIM_ChnInit.TIMER_CH_Mode = TIMER_CH_MODE_PWM;
sTIM_ChnInit.TIMER_CH_REF_Format = TIMER_CH_REF_Format3;
TIMER_ChnInit(MDR_TIMER1, &sTIM_ChnInit);
TIMER_SetChnCompare(MDR_TIMER1, TIMER_CHANNEL1, 0x100);
/* Initializes the TIMER1 Channel1 Output -------------------------------*/
TIMER_ChnOutStructInit(&sTIM_ChnOutInit);
sTIM_ChnOutInit.TIMER_CH_Number = TIMER_CHANNEL1;
sTIM_ChnOutInit.TIMER_CH_DirOut_Polarity = TIMER_CHOPolarity_NonInverted;
sTIM_ChnOutInit.TIMER_CH_DirOut_Source = TIMER_CH_OutSrc_REF;
sTIM_ChnOutInit.TIMER_CH_DirOut_Mode = TIMER_CH_OutMode_Output;
TIMER_ChnOutInit(MDR_TIMER1, &sTIM_ChnOutInit);
/* Initializes the TIMER1 Channel2 -------------------------------------*/
TIMER_ChnStructInit(&sTIM_ChnInit);
sTIM_ChnInit.TIMER_CH_Number = TIMER_CHANNEL2;
sTIM_ChnInit.TIMER_CH_Mode = TIMER_CH_MODE_CAPTURE;
TIMER_ChnInit(MDR_TIMER1, &sTIM_ChnInit);
/* Initializes the TIMER1 Channel2 Output -------------------------------*/
TIMER_ChnOutStructInit(&sTIM_ChnOutInit);
sTIM_ChnOutInit.TIMER_CH_Number = TIMER_CHANNEL2;
sTIM_ChnOutInit.TIMER_CH_DirOut_Polarity = TIMER_CHOPolarity_NonInverted;
sTIM_ChnOutInit.TIMER_CH_DirOut_Source = TIMER_CH_OutSrc_Only_0;
sTIM_ChnOutInit.TIMER_CH_DirOut_Mode = TIMER_CH_OutMode_Input;
TIMER_ChnOutInit(MDR_TIMER1, &sTIM_ChnOutInit);
/* Enable TIMER1 DMA request */
TIMER_DMACmd(MDR_TIMER1,(TIMER_STATUS_CCR_CAP_CH2), ENABLE);
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* DMA_Channel_TIM1 configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_TIMER1->CCR2));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf;
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncHalfword;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic;
DMA_PriCtrlStr.DMA_CycleSize = BufferSize;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_High;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel */
DMA_Init(DMA_Channel_TIM1, &DMA_InitStr);
/* Enable TIMER1 */
TIMER_Cmd(MDR_TIMER1,ENABLE);
/* Transfer complete */
while((DMA_GetFlagStatus(DMA_Channel_TIM1, DMA_FLAG_CHNL_ENA)))
{
}
/* Check the corectness of written dada */
for(i = 0; i < BufferSize; i++)
{
if (DstBuf[i] != MDR_TIMER1->CCR1)
{
TransferStatus &= FAILED;
break;
}
else
{
TransferStatus = PASSED;
}
}
/* TransferStatus = PASSED, if the data transmitted are correct */
/* TransferStatus = FAILED, if the data transmitted are not correct */
while(1)
{
}
}
void main(void)
#endif
{
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_SSP1 | RST_CLK_PCLK_SSP2 | RST_CLK_PCLK_DMA),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_PORTF | RST_CLK_PCLK_PORTD), ENABLE);
/* Init NVIC */
SCB->AIRCR = 0x05FA0000 | ((uint32_t)0x500);
SCB->VTOR = 0x08000000;
/* Disable all interrupt */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICER[0] = 0xFFFFFFFF;
/* Disable all DMA request */
MDR_DMA->CHNL_REQ_MASK_CLR = 0xFFFFFFFF;
MDR_DMA->CHNL_USEBURST_CLR = 0xFFFFFFFF;
/* Reset PORTD settings */
PORT_DeInit(MDR_PORTD);
/* Reset PORTF settings */
PORT_DeInit(MDR_PORTF);
/* Configure SSP2 pins: FSS, CLK, RXD, TXD */
/* Configure PORTD pins 2, 3, 5, 6 */
PORT_InitStructure.PORT_Pin = (PORT_Pin_2 | PORT_Pin_3 | PORT_Pin_5);
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_ALTER;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_FAST;
PORT_Init(MDR_PORTD, &PORT_InitStructure);
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_Pin = (PORT_Pin_6);
PORT_Init(MDR_PORTD, &PORT_InitStructure);
/* Configure SSP1 pins: FSS, CLK, RXD, TXD */
/* Configure PORTF pins 0, 1, 2, 3 */
PORT_InitStructure.PORT_Pin = (PORT_Pin_3);
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_Init(MDR_PORTF, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = (PORT_Pin_0 | PORT_Pin_1 | PORT_Pin_2);
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_Init(MDR_PORTF, &PORT_InitStructure);
/* Init RAM */
Init_RAM (DstBuf1, BufferSize);
Init_RAM (SrcBuf1, BufferSize);
Init_RAM (DstBuf2, BufferSize);
Init_RAM (SrcBuf2, BufferSize);
/* Reset all SSP settings */
SSP_DeInit(MDR_SSP1);
SSP_DeInit(MDR_SSP2);
SSP_BRGInit(MDR_SSP1,SSP_HCLKdiv16);
SSP_BRGInit(MDR_SSP2,SSP_HCLKdiv16);
/* SSP1 MASTER configuration ------------------------------------------------*/
SSP_StructInit (&sSSP);
sSSP.SSP_SCR = 0x10;
sSSP.SSP_CPSDVSR = 2;
sSSP.SSP_Mode = SSP_ModeMaster;
sSSP.SSP_WordLength = SSP_WordLength16b;
sSSP.SSP_SPH = SSP_SPH_1Edge;
sSSP.SSP_SPO = SSP_SPO_Low;
sSSP.SSP_FRF = SSP_FRF_SPI_Motorola;
sSSP.SSP_HardwareFlowControl = SSP_HardwareFlowControl_SSE;
SSP_Init (MDR_SSP1,&sSSP);
/* SSP2 SLAVE configuration ------------------------------------------------*/
sSSP.SSP_SPH = SSP_SPH_1Edge;
sSSP.SSP_SPO = SSP_SPO_Low;
sSSP.SSP_CPSDVSR = 12;
sSSP.SSP_Mode = SSP_ModeSlave;
SSP_Init (MDR_SSP2,&sSSP);
/* Enable SSP1 DMA Rx and Tx request */
SSP_DMACmd(MDR_SSP1,(SSP_DMA_RXE | SSP_DMA_TXE), ENABLE);
/* Enable SSP2 DMA Rx and Tx request */
SSP_DMACmd(MDR_SSP2,(SSP_DMA_RXE | SSP_DMA_TXE), ENABLE);
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* DMA_Channel_SSP1_RX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_SSP1->DR));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf1;
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncHalfword;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic;
DMA_PriCtrlStr.DMA_CycleSize = BufferSize;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_4;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_High;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP1_RX, &DMA_InitStr);
/* DMA_Channel_SSP2_RX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_SSP2->DR));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf2;
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP2_RX, &DMA_InitStr);
/* DMA_Channel_SSP1_TX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)SrcBuf1;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_SSP1->DR));
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncHalfword;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_InitStr.DMA_Priority = DMA_Priority_Default;
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP1_TX, &DMA_InitStr);
/* DMA_Channel_SSP2_TX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)SrcBuf2;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_SSP2->DR));
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP2_TX, &DMA_InitStr);
/* Enable SSP1 */
SSP_Cmd(MDR_SSP1, ENABLE);
/* Enable SSP2 */
SSP_Cmd(MDR_SSP2, ENABLE);
/* Transfer complete */
while((SSP_GetFlagStatus(MDR_SSP1, SSP_FLAG_BSY)))
{
}
while((SSP_GetFlagStatus(MDR_SSP2, SSP_FLAG_BSY)))
{
}
/* Check the corectness of written dada */
TransferStatus1 = Verif_mem ((BufferSize), SrcBuf1, DstBuf2);
TransferStatus2 = Verif_mem ((BufferSize), SrcBuf2, DstBuf1);
/* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received
are correct */
/* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received
are different */
while(1)
{
}
}
void main(void)
#endif
{
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSIdiv2, 0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd(
(RST_CLK_PCLK_RST_CLK |
RST_CLK_PCLK_UART1 |
RST_CLK_PCLK_UART2 |
RST_CLK_PCLK_DMA),
ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_PORTC | RST_CLK_PCLK_PORTD), ENABLE);
/* Disable all DMA request */
MDR_DMA ->CHNL_REQ_MASK_CLR = 0xFFFFFFFF;
MDR_DMA ->CHNL_USEBURST_CLR = 0xFFFFFFFF;
/* Reset PORTC settings */
PORT_DeInit(MDR_PORTC );
/* Reset PORTC settings */
PORT_DeInit(MDR_PORTD );
/* Configure UART1 pins: RXD, TXD */
/* Configure PORTB pins 3, 4 */
PORT_InitStructure.PORT_Pin = PORT_Pin_4;
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_MAIN;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_FAST;
PORT_Init(MDR_PORTC, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = PORT_Pin_3;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_Init(MDR_PORTC, &PORT_InitStructure);
/* Configure UART2 pins: RXD, TXD */
/* Configure PORTF pins 13, 14 */
PORT_InitStructure.PORT_Pin = PORT_Pin_14;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_MAIN;
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_Init(MDR_PORTD, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = (PORT_Pin_13);
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_Init(MDR_PORTD, &PORT_InitStructure);
/* Init RAM */
Init_RAM(DstBuf1, BufferSize);
Init_RAM(SrcBuf1, BufferSize);
Init_RAM(DstBuf2, BufferSize);
Init_RAM(SrcBuf2, BufferSize);
/* Reset all UART settings */
UART_DeInit(MDR_UART1 );
UART_DeInit(MDR_UART2 );
UART_BRGInit(MDR_UART1, UART_HCLKdiv1 );
UART_BRGInit(MDR_UART2, UART_HCLKdiv1 );
/* UART1 configuration ------------------------------------------------*/
UART_StructInit(&sUART);
sUART.UART_BaudRate = 1200;
sUART.UART_WordLength = UART_WordLength8b;
sUART.UART_StopBits = UART_StopBits1;
sUART.UART_Parity = UART_Parity_No;
sUART.UART_FIFOMode = UART_FIFO_ON;
sUART.UART_HardwareFlowControl = (UART_HardwareFlowControl_RXE
| UART_HardwareFlowControl_TXE );
UART_Init(MDR_UART1, &sUART);
UART_DMAConfig( MDR_UART1,
UART_IT_FIFO_LVL_8words,
UART_IT_FIFO_LVL_8words );
/* UART2 configuration ------------------------------------------------*/
UART_Init(MDR_UART2, &sUART);
UART_DMAConfig(MDR_UART2,
UART_IT_FIFO_LVL_8words,
UART_IT_FIFO_LVL_8words );
/* Enable UART1 DMA Rx and Tx request */
UART_DMACmd(MDR_UART1, (UART_DMA_RXE | UART_DMA_TXE ), ENABLE);
/* Enable UART2 DMA Rx and Tx request */
UART_DMACmd(MDR_UART2, (UART_DMA_RXE | UART_DMA_TXE ), ENABLE);
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* DMA_Channel_UART1_RX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t) (&(MDR_UART1 ->DR));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t) DstBuf1;
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncByte;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic;
DMA_PriCtrlStr.DMA_CycleSize = BufferSize;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_8;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_High;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel */
DMA_Init(DMA_Channel_REQ_UART1_RX, &DMA_InitStr);
/* DMA_Channel_UART2_RX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t) (&(MDR_UART2 ->DR));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t) DstBuf2;
/* Init DMA channel */
DMA_Init(DMA_Channel_REQ_UART2_RX, &DMA_InitStr);
/* DMA_Channel_UART1_TX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t) SrcBuf1;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t) (&(MDR_UART1 ->DR));
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncByte;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_InitStr.DMA_Priority = DMA_Priority_Default;
/* Init DMA channel */
DMA_Init(DMA_Channel_REQ_UART1_TX, &DMA_InitStr);
/* DMA_Channel_UART2_TX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t) SrcBuf2;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t) (&(MDR_UART2 ->DR));
/* Init DMA channel */
DMA_Init(DMA_Channel_REQ_UART2_TX, &DMA_InitStr);
/* Enable UART1 */
UART_Cmd(MDR_UART1, ENABLE);
/* Enable UART2 */
UART_Cmd(MDR_UART2, ENABLE);
/* Transfer complete */
while ((DMA_GetFlagStatus(DMA_Channel_REQ_UART1_TX, DMA_FLAG_CHNL_ENA )));
while ((DMA_GetFlagStatus(DMA_Channel_REQ_UART1_RX, DMA_FLAG_CHNL_ENA )));
while ((DMA_GetFlagStatus(DMA_Channel_REQ_UART2_TX, DMA_FLAG_CHNL_ENA )));
while ((DMA_GetFlagStatus(DMA_Channel_REQ_UART2_RX, DMA_FLAG_CHNL_ENA )));
/* Check the corectness of written dada */
TransferStatus1 = Verif_mem((BufferSize / 2), SrcBuf1, DstBuf2);
TransferStatus2 = Verif_mem((BufferSize / 2), SrcBuf2, DstBuf1);
/* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received
are correct */
/* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received
are different */
while (1);
}
void main(void)
#endif
{
DMA_ChannelInitTypeDef DMA_InitStr;
DMA_CtrlDataInitTypeDef DMA_PriCtrlStr;
DMA_CtrlDataInitTypeDef DMA_AltCtrlStr;
uint32_t DMA_Channel = 3;
RST_CLK_DeInit();
RST_CLK_PCLKcmd(RST_CLK_PCLK_DMA, ENABLE);
/* Init RAM */
Init_RAM (DestBuf, SIZE);
Init_RAM (PriBuf, SIZE);
Init_RAM (AltBuf, SIZE);
/* Reset all settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)PriBuf;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DestBuf;
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncWord;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncWord;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic;
DMA_PriCtrlStr.DMA_CycleSize = SIZE;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_16;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Alternate Control Data */
DMA_AltCtrlStr.DMA_SourceBaseAddr = (uint32_t)AltBuf;
DMA_AltCtrlStr.DMA_DestBaseAddr = (uint32_t)DestBuf;
DMA_AltCtrlStr.DMA_SourceIncSize = DMA_SourceIncWord;
DMA_AltCtrlStr.DMA_DestIncSize = DMA_DestIncWord;
DMA_AltCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
DMA_AltCtrlStr.DMA_Mode = DMA_Mode_AutoRequest;
DMA_AltCtrlStr.DMA_CycleSize = SIZE;
DMA_AltCtrlStr.DMA_NumContinuous = DMA_Transfers_16;
DMA_AltCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_AltCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_AltCtrlData = &DMA_AltCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_Default;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel */
DMA_Init(DMA_Channel, &DMA_InitStr);
/* Run channel */
DMA_Cmd(DMA_Channel, ENABLE);
DMA_Request(DMA_Channel);
/* Transfer complete */
while (DMA_GetFlagStatus(DMA_Channel, DMA_FLAG_CHNL_ENA))
{
if((MDR_DMA->STATUS & 0x000000F0)==0x00000000)
{
DMA_Request(DMA_Channel);
}
}
/* Check the corectness of written data */
TransferStatus1 = Verif_mem(SIZE, PriBuf, DestBuf);
/* TransferStatus1 = PASSED, if the data transmitted and received are correct */
/* TransferStatus1 = FAILED, if the data transmitted and received are different */
/* Set Channel Structure */
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_ALTERNATE;
/* Init DMA channel */
DMA_Init(DMA_Channel, &DMA_InitStr);
/* Run channel */
DMA_Cmd(DMA_Channel, ENABLE);
DMA_Request(DMA_Channel);
/* Transfer complete */
while (DMA_GetFlagStatus(DMA_Channel, DMA_FLAG_CHNL_ENA))
{
}
/* Check the corectness of written data */
TransferStatus2 = Verif_mem(SIZE, AltBuf, DestBuf);
/* TransferStatus2 = PASSED, if the data transmitted and received are correct */
/* TransferStatus2 = FAILED, if the data transmitted and received are different */
while (1)
{
}
}
