void mdma_configure_interrupts(volatile avr32_mdma_t *mdma, const mdma_interrupt_t *bitfield)
{
bool global_interrupt_enabled = Is_global_interrupt_enabled();
// Enable the appropriate interrupts.
mdma->ier = bitfield->ch0c << AVR32_MDMA_IER_CH0C_OFFSET |
bitfield->ch1c << AVR32_MDMA_IER_CH1C_OFFSET |
bitfield->ch2c << AVR32_MDMA_IER_CH2C_OFFSET |
bitfield->ch3c << AVR32_MDMA_IER_CH3C_OFFSET |
bitfield->berr0 << AVR32_MDMA_IER_BERR0_OFFSET |
bitfield->berr1 << AVR32_MDMA_IER_BERR1_OFFSET |
bitfield->berr2 << AVR32_MDMA_IER_BERR2_OFFSET |
bitfield->berr3 << AVR32_MDMA_IER_BERR3_OFFSET ;
// Disable the appropriate interrupts.
if (global_interrupt_enabled) Disable_global_interrupt();
mdma->idr = (~bitfield->ch0c & 1) << AVR32_MDMA_IDR_CH0C_OFFSET |
(~bitfield->ch1c & 1) << AVR32_MDMA_IDR_CH1C_OFFSET |
(~bitfield->ch2c & 1) << AVR32_MDMA_IDR_CH2C_OFFSET |
(~bitfield->ch3c & 1) << AVR32_MDMA_IDR_CH3C_OFFSET |
(~bitfield->berr0 & 1) << AVR32_MDMA_IDR_BERR0_OFFSET |
(~bitfield->berr1 & 1) << AVR32_MDMA_IDR_BERR1_OFFSET |
(~bitfield->berr2 & 1) << AVR32_MDMA_IDR_BERR2_OFFSET |
(~bitfield->berr3 & 1) << AVR32_MDMA_IDR_BERR3_OFFSET ;
if (global_interrupt_enabled) Enable_global_interrupt();
}
int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield)
{
bool global_interrupt_enabled = Is_global_interrupt_enabled();
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// Enable the appropriate interrupts.
tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET |
bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET |
bitfield->ldras << AVR32_TC_LDRAS_OFFSET |
bitfield->cpcs << AVR32_TC_CPCS_OFFSET |
bitfield->cpbs << AVR32_TC_CPBS_OFFSET |
bitfield->cpas << AVR32_TC_CPAS_OFFSET |
bitfield->lovrs << AVR32_TC_LOVRS_OFFSET |
bitfield->covfs << AVR32_TC_COVFS_OFFSET;
// Disable the appropriate interrupts.
if (global_interrupt_enabled) Disable_global_interrupt();
tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET |
(~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET |
(~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET |
(~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET |
(~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET |
(~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET |
(~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET |
(~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET;
tc->channel[channel].sr;
if (global_interrupt_enabled) Enable_global_interrupt();
return 0;
}
void twim_disable_interrupt(volatile avr32_twim_t *twi)
{
bool global_interrupt_enabled = Is_global_interrupt_enabled();
if (global_interrupt_enabled) Disable_global_interrupt();
twi->idr = ~0UL;
twi->scr = ~0UL;
}
void eic_clear_interrupt_lines(volatile avr32_eic_t *eic, unsigned int mask_lines)
{
Bool global_interrupt_enabled = Is_global_interrupt_enabled();
if (global_interrupt_enabled) Disable_global_interrupt();
eic->icr = mask_lines;
eic->isr;
if (global_interrupt_enabled) Enable_global_interrupt();
}
void pm_bod_disable_irq(volatile avr32_pm_t *pm)
{
Bool global_interrupt_enabled = Is_global_interrupt_enabled();
if (global_interrupt_enabled) Disable_global_interrupt();
pm->idr = AVR32_PM_IDR_BODDET_MASK;
pm->isr;
if (global_interrupt_enabled) Enable_global_interrupt();
}
void eic_clear_interrupt_line(volatile avr32_eic_t *eic, unsigned int line_number)
{
Bool global_interrupt_enabled = Is_global_interrupt_enabled();
// Clear line line_number
if (global_interrupt_enabled) Disable_global_interrupt();
eic->icr = 1 << line_number;
eic->isr;
if (global_interrupt_enabled) Enable_global_interrupt();
}
int twi_slave_init(volatile avr32_twi_t *twi, const twi_options_t *opt, const twi_slave_fct_t *slave_fct)
{
bool global_interrupt_enabled = Is_global_interrupt_enabled();
// Set pointer to TWIM instance for IT
twi_inst = twi;
// Disable TWI interrupts
if (global_interrupt_enabled) Disable_global_interrupt();
twi->idr = ~0UL;
twi->sr;
// Reset TWI
twi->cr = AVR32_TWI_CR_SWRST_MASK;
if (global_interrupt_enabled) Enable_global_interrupt();
// Dummy read in SR
twi->sr;
// Disable all interrupts
Disable_global_interrupt();
// Register TWI handler on level 2
INTC_register_interrupt( &twi_slave_interrupt_handler, AVR32_TWI_IRQ, AVR32_INTC_INT1);
// Enable all interrupts
Enable_global_interrupt();
// Set slave address
twi->smr = (opt->chip << AVR32_TWI_SMR_SADR_OFFSET);
// Disable master transfer
twi->cr = AVR32_TWI_CR_MSDIS_MASK;
// Enable slave
twi->cr = AVR32_TWI_CR_SVEN_MASK;
// get a pointer to applicative routines
twi_slave_fct = *slave_fct;
// Slave Access Interrupt Enable
twi_it_mask = AVR32_TWI_IER_SVACC_MASK;
twi->ier = twi_it_mask;
// Everything went ok
return TWI_SUCCESS;
}
void vDisableMACBOperations(volatile avr32_macb_t *macb)
{
bool global_interrupt_enabled = Is_global_interrupt_enabled();
#if ETHERNET_CONF_USE_PHY_IT == 1
volatile avr32_gpio_t *gpio = &AVR32_GPIO;
volatile avr32_gpio_port_t *gpio_port = &gpio->port[EXTPHY_MACB_INTERRUPT_PIN/32];
gpio_port->ierc = 1 << (EXTPHY_MACB_INTERRUPT_PIN%32);
#endif
// write the MACB control register : disable Tx & Rx
macb->ncr &= ~((1 << AVR32_MACB_RE_OFFSET) | (1 << AVR32_MACB_TE_OFFSET));
// We no more want to interrupt on Rx and Tx events.
if (global_interrupt_enabled) Disable_global_interrupt();
macb->idr = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK;
macb->isr;
if (global_interrupt_enabled) Enable_global_interrupt();
}
int twi_master_init(volatile avr32_twim_t *twi, const twi_options_t *opt) {
bool global_interrupt_enabled = Is_global_interrupt_enabled();
int status = TWI_SUCCESS;
// Disable TWI interrupts
if (global_interrupt_enabled) Disable_global_interrupt();
twi->idr = ~0UL;
// Reset TWI
twi->cr = AVR32_TWIM_CR_SWRST_MASK;
if (global_interrupt_enabled) Enable_global_interrupt();
// Clear SR
twi->scr = ~0UL;
// Disable all interrupts
Disable_global_interrupt();
// Register TWI handler on level 2
BSP_INTC_IntReg( &twi_master_interrupt_handler, AVR32_TWIM0_IRQ, AVR32_INTC_INT1);
// Enable all interrupts
Enable_global_interrupt();
twi->cr = AVR32_TWIM_CR_MEN_MASK;
if (opt->smbus) {
twi->cr = AVR32_TWIM_CR_SMEN_MASK;
twi->smbtr = (unsigned long) -1;
}
// Select the speed
if (twi_set_speed(twi, opt->speed, opt->pba_hz) == TWI_INVALID_CLOCK_DIV)
return TWI_INVALID_CLOCK_DIV;
// Probe the component
//status = twi_probe(twi, opt->chip);
return status;
}
//! host_disable_all_pipes
//!
//! This function disables all pipes for the host controller.
//! Useful to execute upon disconnection.
//!
//! @return Void
//!
void host_disable_all_pipes(void)
{
#if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE
Bool sav_glob_int_en;
#endif
U8 p;
#if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE
if ((sav_glob_int_en = Is_global_interrupt_enabled())) Disable_global_interrupt();
#endif
for (p = 0; p < MAX_PEP_NB; p++)
{
Host_disable_pipe_interrupt(p);
Host_reset_pipe(p);
Host_unallocate_memory(p);
Host_disable_pipe(p);
}
#if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE
(void)Is_host_pipe_enabled(MAX_PEP_NB - 1);
if (sav_glob_int_en) Enable_global_interrupt();
#endif
}
int twi_master_init(volatile avr32_twi_t *twi, const twi_options_t *opt)
{
bool global_interrupt_enabled = Is_global_interrupt_enabled();
int status = TWI_SUCCESS;
// Set pointer to TWIM instance for IT
twi_inst = twi;
// Disable TWI interrupts
if (global_interrupt_enabled) Disable_global_interrupt();
twi->idr = ~0UL;
twi->sr;
// Reset TWI
twi->cr = AVR32_TWI_CR_SWRST_MASK;
if (global_interrupt_enabled) Enable_global_interrupt();
// Dummy read in SR
twi->sr;
// Disable all interrupts
Disable_global_interrupt();
// Register TWI handler on level 2
INTC_register_interrupt( &twi_master_interrupt_handler, AVR32_TWI_IRQ, AVR32_INTC_INT1);
// Enable all interrupts
Enable_global_interrupt();
// Select the speed
twi_set_speed(twi, opt->speed, opt->pba_hz);
// Probe the component
//status = twi_probe(twi, opt->chip);
return status;
}
int pwm_init(const pwm_opt_t *opt)
{
volatile avr32_pwm_t *pwm = &AVR32_PWM;
Bool global_interrupt_enabled = Is_global_interrupt_enabled();
if (opt == 0 ) // Null pointer.
return PWM_INVALID_INPUT;
// Disable interrupt.
if (global_interrupt_enabled) Disable_global_interrupt();
pwm->idr = ((1 << (AVR32_PWM_LINES_MSB + 1)) - 1) << AVR32_PWM_IDR_CHID0_OFFSET;
pwm->isr;
if (global_interrupt_enabled) Enable_global_interrupt();
// Set PWM mode register.
pwm->mr =
((opt->diva)<<AVR32_PWM_DIVA_OFFSET) |
((opt->divb)<<AVR32_PWM_DIVB_OFFSET) |
((opt->prea)<<AVR32_PWM_PREA_OFFSET) |
((opt->preb)<<AVR32_PWM_PREB_OFFSET)
;
return PWM_SUCCESS;
}
//! host_disable_all_pipes
//!
//! This function disables all pipes for the host controller.
//! Useful to execute upon disconnection.
//!
//! @return Void
//!
void host_disable_all_pipes(void)
{
#if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE
Bool sav_glob_int_en;
#endif
U8 p;
#if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE
// Disable global interrupts
if ((sav_glob_int_en = Is_global_interrupt_enabled())) Disable_global_interrupt();
#endif
for (p = 0; p < MAX_PEP_NB; p++)
{ // Disable the pipe <p> (disable interrupt, free memory, reset pipe, ...)
Host_disable_pipe_interrupt(p);
Host_reset_pipe(p);
Host_unallocate_memory(p);
Host_disable_pipe(p);
}
#if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE
(void)Is_host_pipe_enabled(MAX_PEP_NB - 1);
// Restore the global interrupts to the initial state
if (sav_glob_int_en) Enable_global_interrupt();
#endif
}
void aic23b_dac_start(uint32_t sample_rate_hz,
uint8_t num_channels,
uint8_t bits_per_sample,
bool swap_channels,
void (*callback)(uint32_t arg),
uint32_t callback_opt,
uint32_t pba_hz)
{
#if AIC23B_CTRL_INTERFACE == AIC23B_CTRL_INTERFACE_SPI
static const spi_options_t AIC23B_SPI_OPTIONS =
{
.reg = AIC23B_SPI_NPCS,
.baudrate = AIC23B_SPI_MASTER_SPEED,
.bits = AIC23B_CTRL_SIZE,
.spck_delay = 0,
.trans_delay = 0,
.stay_act = 0,
.spi_mode = 3,
.modfdis = 1
};
spi_setupChipReg(AIC23B_SPI, &AIC23B_SPI_OPTIONS, pba_hz);
#endif
aic23b_dac_stop();
gpio_enable_module(AIC23B_SSC_DAC_GPIO_MAP,
sizeof(AIC23B_SSC_DAC_GPIO_MAP) / sizeof(AIC23B_SSC_DAC_GPIO_MAP[0]));
aic23b_pdc_t pdc;
pdc.data = AIC23B_DEFAULT(AIC23B_PDC);
pdc.off = 0;
pdc.clk = 0;
pdc.osc = 0;
pdc.out = 0;
pdc.dac = 0;
pdc.adc = 1;
pdc.mic = 1;
pdc.line = 1;
aic23b_set_power_down_state(pdc);
aic23b_dac_setup(sample_rate_hz,
num_channels,
bits_per_sample,
swap_channels,
callback,
callback_opt,
pba_hz);
aic23b_aapc_t aapc;
aapc.data = AIC23B_DEFAULT(AIC23B_AAPC);
aapc.ste = 0;
aapc.dac = 1;
aapc.byp = 0;
aapc.micm = 1;
aapc.micb = 0;
aic23b_set_analog_audio_path(aapc);
aic23b_dapc_t dapc;
dapc.data = AIC23B_DEFAULT(AIC23B_DAPC);
dapc.dacm = 0;
dapc.deemp = AIC23B_DAPC_DEEMP_NONE;
dapc.adchp = 1;
aic23b_set_digital_audio_path(dapc);
// set an acceptable start volume
aic23b_set_headphone_volume(AIC23B_LEFT_CHANNEL | AIC23B_RIGHT_CHANNEL,
-30,
true);
aic23b_activate_dig_audio(true);
INTC_register_interrupt(&aic23b_ssc_tx_pdca_int_handler,
AIC23B_SSC_TX_PDCA_IRQ,
AIC23B_SSC_TX_PDCA_INT_LEVEL);
}
void aic23b_dac_setup(uint32_t sample_rate_hz,
uint8_t num_channels,
uint8_t bits_per_sample,
bool swap_channels,
void (*callback)(uint32_t arg),
uint32_t callback_opt,
uint32_t pba_hz)
{
#if defined(AIC23B_DAC_USE_RX_CLOCK) && AIC23B_DAC_USE_RX_CLOCK == true
#if defined(AIC23B_DAC_RX_CLOCK_SET_CALLBACK)
AIC23B_DAC_RX_CLOCK_SET_CALLBACK(2 * sample_rate_hz *
((bits_per_sample <= 16) ? 16 :
(bits_per_sample <= 20) ? 20 :
(bits_per_sample <= 24) ? 24 :
32));
#endif
ssc_i2s_init(AIC23B_SSC,
sample_rate_hz,
bits_per_sample,
(bits_per_sample <= 16) ? 16 :
(bits_per_sample <= 20) ? 20 :
(bits_per_sample <= 24) ? 24 :
32,
SSC_I2S_MODE_STEREO_OUT_EXT_CLK,
pba_hz);
#else
ssc_i2s_init(AIC23B_SSC,
sample_rate_hz,
bits_per_sample,
(bits_per_sample <= 16) ? 16 :
(bits_per_sample <= 20) ? 20 :
(bits_per_sample <= 24) ? 24 :
32,
SSC_I2S_MODE_STEREO_OUT,
pba_hz);
#endif
pdca_channel_options_t aic23b_ssc_pdca_options =
{
.addr = NULL,
.size = 0,
.r_addr = NULL,
.r_size = 0,
.pid = AIC23B_SSC_TX_PDCA_PID,
.transfer_size = (bits_per_sample <= 8) ? PDCA_TRANSFER_SIZE_BYTE :
(bits_per_sample <= 16) ? PDCA_TRANSFER_SIZE_HALF_WORD :
PDCA_TRANSFER_SIZE_WORD
};
pdca_init_channel(AIC23B_SSC_TX_PDCA_CHANNEL, &aic23b_ssc_pdca_options);
pdca_enable(AIC23B_SSC_TX_PDCA_CHANNEL);
#if !defined(AIC23B_DAC_USE_RX_CLOCK) || AIC23B_DAC_USE_RX_CLOCK == false || \
!defined(AIC23B_DAC_RX_CLOCK_SET_CALLBACK)
// Set DAC frequency
aic23b_configure_freq(AIC23B_MCLK_HZ, sample_rate_hz);
#endif
aic23b_daif_t daif;
daif.data = AIC23B_DEFAULT(AIC23B_DAIF);
daif.ms = AIC23B_DAIF_MS_SLAVE;
daif.lrswap = swap_channels;
daif.lrp = 0;
daif.iwl = (bits_per_sample <= 16) ? AIC23B_DAIF_IWL_16 :
(bits_per_sample <= 20) ? AIC23B_DAIF_IWL_20 :
(bits_per_sample <= 24) ? AIC23B_DAIF_IWL_24 :
AIC23B_DAIF_IWL_32;
daif.fmt = AIC23B_DAIF_FMT_I2S;
aic23b_write_reg(AIC23B_DAIF, daif.data);
aic23b_output_params.num_channels = num_channels;
aic23b_output_params.callback = callback;
aic23b_output_params.callback_opt = callback_opt;
}
#endif
bool aic23b_dac_output(void *sample_buffer, size_t sample_length)
{
bool global_interrupt_enabled;
if (!(pdca_get_transfer_status(AIC23B_SSC_TX_PDCA_CHANNEL) &
PDCA_TRANSFER_COUNTER_RELOAD_IS_ZERO))
return false;
if (sample_length)
{
if (aic23b_output_params.num_channels == 1)
{
int16_t *s16_sample_buffer = sample_buffer;
int i;
for (i = sample_length - 1; i >= 0; i--)
{
s16_sample_buffer[2 * i + 1] =
s16_sample_buffer[2 * i] = s16_sample_buffer[i];
}
}
// The PDCA is not able to synchronize its start of transfer with the SSC
// start of period, so this has to be done by polling the TF pin.
// Not doing so may result in channels being swapped randomly.
if ((global_interrupt_enabled = Is_global_interrupt_enabled()))
Disable_global_interrupt();
if (pdca_get_transfer_status(AIC23B_SSC_TX_PDCA_CHANNEL) &
PDCA_TRANSFER_COMPLETE)
{
while (gpio_get_pin_value(AIC23B_SSC_TX_FRAME_SYNC_PIN));
while (!gpio_get_pin_value(AIC23B_SSC_TX_FRAME_SYNC_PIN));
}
pdca_reload_channel(AIC23B_SSC_TX_PDCA_CHANNEL, sample_buffer, sample_length * 2);
pdca_get_reload_size(AIC23B_SSC_TX_PDCA_CHANNEL);
if (global_interrupt_enabled)
Enable_global_interrupt();
if (aic23b_output_params.callback_opt & AUDIO_DAC_OUT_OF_SAMPLE_CB)
pdca_enable_interrupt_transfer_complete(AIC23B_SSC_TX_PDCA_CHANNEL);
if (aic23b_output_params.callback_opt & AUDIO_DAC_RELOAD_CB)
pdca_enable_interrupt_reload_counter_zero(AIC23B_SSC_TX_PDCA_CHANNEL);
}
return true;
}
void ms3_dac_setup(U32 sample_rate_hz, U8 num_channels, U8 bits_per_sample,
bool swap_channels, void (*callback)(U32 arg), U32 callback_opt,
U32 pba_hz)
{
//configure clock
if (sample_rate_hz < (8000 + 8021) / 2) {
usb_stream_resync_frequency = 4096000;
cs2200_freq_clk_out(_32_BITS_RATIO(usb_stream_resync_frequency, CS2200_FREF));
}
else if (sample_rate_hz < (8021 + 22050) / 2) {
usb_stream_resync_frequency = 4106752;
cs2200_freq_clk_out(_32_BITS_RATIO(usb_stream_resync_frequency, CS2200_FREF));
}
else if (sample_rate_hz < (22050 + 32000) / 2) {
usb_stream_resync_frequency = 11289600;
cs2200_freq_clk_out(_32_BITS_RATIO(usb_stream_resync_frequency, CS2200_FREF));
}
else if (sample_rate_hz < (32000 + 44100) / 2) {
usb_stream_resync_frequency = 16384000;
cs2200_freq_clk_out(_32_BITS_RATIO(usb_stream_resync_frequency, CS2200_FREF));
}
else if (sample_rate_hz < (44100 + 48000) / 2) {
usb_stream_resync_frequency = 22579200;
cs2200_freq_clk_out(_32_BITS_RATIO(usb_stream_resync_frequency, CS2200_FREF));
}
else if (sample_rate_hz < (48000 + 88200) / 2) {
usb_stream_resync_frequency = 24576000;
cs2200_freq_clk_out(_32_BITS_RATIO(usb_stream_resync_frequency, CS2200_FREF));
}
//configure ssc to use clock on TX_CLOCK pin
AVR32_SSC.tcmr = (0 << AVR32_SSC_TCMR_CKO_OFFSET)
| (1 << AVR32_SSC_TCMR_STTDLY_OFFSET)
| (2 << AVR32_SSC_TCMR_CKS_OFFSET)
| (7 << AVR32_SSC_TCMR_START_OFFSET)
| (0x1f << AVR32_SSC_TCMR_PERIOD_OFFSET);
AVR32_SSC.tfmr = (0xf << AVR32_SSC_TFMR_DATLEN_OFFSET)
| (1 << AVR32_SSC_TFMR_MSBF_OFFSET)
| (1 << AVR32_SSC_TFMR_FSOS_OFFSET)
| (1 << AVR32_SSC_TFMR_FSLENHI_OFFSET)
| (0xf << AVR32_SSC_TFMR_FSLEN_OFFSET);
AVR32_SSC.cr = AVR32_SSC_CR_TXEN_MASK;
//configure DMA
pdca_channel_options_t ms3_ssc_pdca_options = {
.addr = NULL,
.size = 0,
.r_addr = NULL,
.r_size = 0,
.pid = AVR32_PDCA_PID_SSC_TX,
.transfer_size = (bits_per_sample <= 8)?PDCA_TRANSFER_SIZE_BYTE:
(bits_per_sample <= 16)?PDCA_TRANSFER_SIZE_HALF_WORD:
PDCA_TRANSFER_SIZE_WORD
};
pdca_init_channel(MS3_SSC_TX_PDCA_CHANNEL, &ms3_ssc_pdca_options);
pdca_enable(MS3_SSC_TX_PDCA_CHANNEL);
//configure audio parameters
ms3_output_params.num_channels = num_channels;
ms3_output_params.callback = callback;
ms3_output_params.callback_opt = callback_opt;
}
bool ms3_dac_output(void *sample_buffer, size_t sample_length)
{
bool global_interrupt_enabled;
if (!(pdca_get_transfer_status(MS3_SSC_TX_PDCA_CHANNEL) &
PDCA_TRANSFER_COUNTER_RELOAD_IS_ZERO))
return false;
if (sample_length) {
if (ms3_output_params.num_channels == 1) {
S16 *s16_sample_buffer = sample_buffer;
int i;
for (i = sample_length - 1; i >= 0; i--) {
s16_sample_buffer[2 * i + 1] =
s16_sample_buffer[2 * i] =
s16_sample_buffer[i];
}
}
// The PDCA is not able to synchronize its start of transfer with the SSC
// start of period, so this has to be done by polling the TF pin.
// Not doing so may result in channels being swapped randomly.
if ((global_interrupt_enabled = Is_global_interrupt_enabled()))
Disable_global_interrupt();
if (pdca_get_transfer_status(MS3_SSC_TX_PDCA_CHANNEL) &
PDCA_TRANSFER_COMPLETE) {
while (gpio_get_pin_value(MS3_SSC_TX_FRAME_SYNC_PIN));
while (!gpio_get_pin_value(MS3_SSC_TX_FRAME_SYNC_PIN));
}
pdca_reload_channel(MS3_SSC_TX_PDCA_CHANNEL, sample_buffer, sample_length * 2);
pdca_get_reload_size(MS3_SSC_TX_PDCA_CHANNEL);
if (global_interrupt_enabled)
Enable_global_interrupt();
if (ms3_output_params.callback_opt & AUDIO_DAC_OUT_OF_SAMPLE_CB)
pdca_enable_interrupt_transfer_complete(MS3_SSC_TX_PDCA_CHANNEL);
if (ms3_output_params.callback_opt & AUDIO_DAC_RELOAD_CB)
pdca_enable_interrupt_reload_counter_zero(MS3_SSC_TX_PDCA_CHANNEL);
}
return true;
}
bool xMACBInit(volatile avr32_macb_t *macb)
{
bool global_interrupt_enabled = Is_global_interrupt_enabled();
volatile unsigned long status;
// generate an hardware reset of the phy
ethernet_phy_hw_reset();
// generate a software reset of the phy
ethernet_phy_sw_reset(macb);
// set up registers
macb->ncr = 0;
macb->tsr = ~0UL;
macb->rsr = ~0UL;
if (global_interrupt_enabled) Disable_global_interrupt();
macb->idr = ~0UL;
status = macb->isr;
if (global_interrupt_enabled) Enable_global_interrupt();
#if ETHERNET_CONF_USE_RMII_INTERFACE
// RMII used, set 0 to the USRIO Register
macb->usrio &= ~AVR32_MACB_RMII_MASK;
#else
// RMII not used, set 1 to the USRIO Register
macb->usrio |= AVR32_MACB_RMII_MASK;
#endif
// Load our MAC address into the MACB.
prvSetupMACAddress(macb);
// Setup the buffers and descriptors.
prvSetupDescriptors(macb);
#if ETHERNET_CONF_SYSTEM_CLOCK <= 20000000
macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV8 << AVR32_MACB_NCFGR_CLK_OFFSET);
#elif ETHERNET_CONF_SYSTEM_CLOCK <= 40000000
macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV16 << AVR32_MACB_NCFGR_CLK_OFFSET);
#elif ETHERNET_CONF_SYSTEM_CLOCK <= 80000000
macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV32 << AVR32_MACB_NCFGR_CLK_OFFSET;
#elif ETHERNET_CONF_SYSTEM_CLOCK <= 160000000
macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV64 << AVR32_MACB_NCFGR_CLK_OFFSET;
#else
# error System clock too fast
#endif
// Are we connected?
if( prvProbePHY(macb) == true )
{
// Enable the interrupt!
portENTER_CRITICAL();
{
prvSetupMACBInterrupt(macb);
}
portEXIT_CRITICAL();
// Enable Rx and Tx, plus the stats register.
macb->ncr = AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
return (true);
}
return (false);
}
//! This function is the generic control pipe management function.
//! This function is used to send and receive control requests over control pipe.
//!
//! @todo Fix all time-out errors and disconnections in active wait loop.
//!
//! @param data_pointer void *: Pointer to data to transfer
//!
//! @return Status_t: Status
//!
//! @note This function uses the usb_request global structure. Hence, this
//! structure should be filled before calling this function.
//!
Status_t host_transfer_control(void *data_pointer)
{
int status = CONTROL_GOOD;
bool sav_int_sof_enable;
bool sav_glob_int_en;
U16 data_length;
U8 c;
Usb_ack_event(EVT_HOST_SOF);
sav_int_sof_enable = Is_host_sof_interrupt_enabled();
Host_enable_sof_interrupt(); // SOF software detection is in interrupt subroutine
while (!Is_usb_event(EVT_HOST_SOF)) // Wait 1 SOF
{
if (Is_host_emergency_exit())
{
Host_freeze_pipe(P_CONTROL);
Host_reset_pipe(P_CONTROL);
status = CONTROL_TIMEOUT;
goto host_transfer_control_end;
}
}
Host_configure_pipe_token(P_CONTROL, TOKEN_SETUP);
Host_ack_setup_ready();
Host_unfreeze_pipe(P_CONTROL);
// Build and send the setup request fields
Host_reset_pipe_fifo_access(P_CONTROL);
Host_write_pipe_data(P_CONTROL, 8, usb_request.bmRequestType);
Host_write_pipe_data(P_CONTROL, 8, usb_request.bRequest);
Host_write_pipe_data(P_CONTROL, 16, usb_format_mcu_to_usb_data(16, usb_request.wValue));
Host_write_pipe_data(P_CONTROL, 16, usb_format_mcu_to_usb_data(16, usb_request.wIndex));
Host_write_pipe_data(P_CONTROL, 16, usb_format_mcu_to_usb_data(16, usb_request.wLength));
Host_send_setup();
while (!Is_host_setup_ready()) // Wait for SETUP ack
{
if (Is_host_emergency_exit())
{
Host_freeze_pipe(P_CONTROL);
Host_reset_pipe(P_CONTROL);
status = CONTROL_TIMEOUT;
goto host_transfer_control_end;
}
if (Is_host_pipe_error(P_CONTROL)) // Any error?
{
c = Host_error_status(P_CONTROL);
Host_ack_all_errors(P_CONTROL);
status = c; // Send error status
goto host_transfer_control_end;
}
}
// Setup token sent; now send IN or OUT token
// Before just wait 1 SOF
Usb_ack_event(EVT_HOST_SOF);
Host_freeze_pipe(P_CONTROL);
data_length = usb_request.wLength;
while (!Is_usb_event(EVT_HOST_SOF)) // Wait 1 SOF
{
if (Is_host_emergency_exit())
{
Host_freeze_pipe(P_CONTROL);
Host_reset_pipe(P_CONTROL);
status = CONTROL_TIMEOUT;
goto host_transfer_control_end;
}
}
// IN request management ---------------------------------------------
if (usb_request.bmRequestType & 0x80) // Data stage IN (bmRequestType.D7 == 1)
{
Host_disable_continuous_in_mode(P_CONTROL);
Host_configure_pipe_token(P_CONTROL, TOKEN_IN);
Host_ack_control_in_received_free();
while (data_length)
{
Host_unfreeze_pipe(P_CONTROL);
private_sof_counter = 0; // Reset the counter in SOF detection subroutine
while (!Is_host_control_in_received())
{
if (Is_host_emergency_exit())
{
Host_freeze_pipe(P_CONTROL);
Host_reset_pipe(P_CONTROL);
status = CONTROL_TIMEOUT;
goto host_transfer_control_end;
}
if (Is_host_pipe_error(P_CONTROL)) // Any error?
{
c = Host_error_status(P_CONTROL);
Host_ack_all_errors(P_CONTROL);
status = c; // Send error status
goto host_transfer_control_end;
}
if (Is_host_stall(P_CONTROL))
{
Host_ack_stall(P_CONTROL);
status = CONTROL_STALL;
goto host_transfer_control_end;
}
#if TIMEOUT_DELAY_ENABLE == ENABLE
if (1000 < host_get_timeout()) // Count 1s
{
Host_freeze_pipe(P_CONTROL);
Host_reset_pipe(P_CONTROL);
status = CONTROL_TIMEOUT;
goto host_transfer_control_end;
}
#endif
}
Host_reset_pipe_fifo_access(P_CONTROL);
c = Host_get_pipe_size(P_CONTROL) - Host_byte_count(P_CONTROL);
data_length = host_read_p_rxpacket(P_CONTROL, data_pointer, data_length, &data_pointer);
if (usb_request.incomplete_read || c) data_length = 0;
Host_freeze_pipe(P_CONTROL);
Host_ack_control_in_received_free();
// In low-speed mode, the USB IP may have not yet sent the ACK at this
// point. The USB IP does not support a new start of transaction request
// from the firmware if the ACK has not been sent. The only means of
// making sure the ACK has been sent is to wait for the next Keep-Alive
// before starting a new transaction.
if (Is_usb_low_speed_mode())
{
Usb_ack_event(EVT_HOST_SOF);
if ((sav_glob_int_en = Is_global_interrupt_enabled())) Disable_global_interrupt();
Host_ack_sof();
(void)Is_host_sof_interrupt_enabled();
if (sav_glob_int_en) Enable_global_interrupt();
Host_enable_sof_interrupt();
while (!Is_usb_event(EVT_HOST_SOF)) // Wait for next Keep-Alive
{
if (Is_host_emergency_exit())
{
Host_freeze_pipe(P_CONTROL);
Host_reset_pipe(P_CONTROL);
status = CONTROL_TIMEOUT;
goto host_transfer_control_end;
}
}
}
} // End of IN data stage
Host_configure_pipe_token(P_CONTROL, TOKEN_OUT);
Host_ack_control_out_ready_send();
Host_unfreeze_pipe(P_CONTROL);
while (!Is_host_control_out_ready())
{
if (Is_host_emergency_exit())
{
Host_freeze_pipe(P_CONTROL);
Host_reset_pipe(P_CONTROL);
status = CONTROL_TIMEOUT;
goto host_transfer_control_end;
}
if (Is_host_pipe_error(P_CONTROL)) // Any error?
{
c = Host_error_status(P_CONTROL);
Host_ack_all_errors(P_CONTROL);
status = c; // Send error status
goto host_transfer_control_end;
}
if (Is_host_stall(P_CONTROL))
{
Host_ack_stall(P_CONTROL);
status = CONTROL_STALL;
goto host_transfer_control_end;
}
}
Host_ack_control_out_ready();
}
// OUT request management --------------------------------------------
else // Data stage OUT (bmRequestType.D7 == 0)
{
Host_configure_pipe_token(P_CONTROL, TOKEN_OUT);
Host_ack_control_out_ready();
while (data_length)
{
Host_unfreeze_pipe(P_CONTROL);
Host_reset_pipe_fifo_access(P_CONTROL);
data_length = host_write_p_txpacket(P_CONTROL, data_pointer, data_length, (const void **)&data_pointer);
Host_send_control_out();
while (!Is_host_control_out_ready())
{
if (Is_host_emergency_exit())
{
Host_freeze_pipe(P_CONTROL);
Host_reset_pipe(P_CONTROL);
status = CONTROL_TIMEOUT;
goto host_transfer_control_end;
}
if (Is_host_pipe_error(P_CONTROL)) // Any error?
{
c = Host_error_status(P_CONTROL);
Host_ack_all_errors(P_CONTROL);
status = c; // Send error status
goto host_transfer_control_end;
}
if (Is_host_stall(P_CONTROL))
{
Host_ack_stall(P_CONTROL);
status = CONTROL_STALL;
goto host_transfer_control_end;
}
}
Host_ack_control_out_ready();
} // End of OUT data stage
Host_freeze_pipe(P_CONTROL);
Host_configure_pipe_token(P_CONTROL, TOKEN_IN);
Host_ack_control_in_received_free();
Host_unfreeze_pipe(P_CONTROL);
while (!Is_host_control_in_received())
{
if (Is_host_emergency_exit())
{
Host_freeze_pipe(P_CONTROL);
Host_reset_pipe(P_CONTROL);
status = CONTROL_TIMEOUT;
goto host_transfer_control_end;
}
if (Is_host_pipe_error(P_CONTROL)) // Any error?
{
c = Host_error_status(P_CONTROL);
Host_ack_all_errors(P_CONTROL);
status = c; // Send error status
goto host_transfer_control_end;
}
if (Is_host_stall(P_CONTROL))
{
Host_ack_stall(P_CONTROL);
status = CONTROL_STALL;
goto host_transfer_control_end;
}
}
Host_ack_control_in_received();
Host_freeze_pipe(P_CONTROL);
Host_free_control_in();
}
host_transfer_control_end:
if (!sav_int_sof_enable) // Restore SOF interrupt enable
{
if ((sav_glob_int_en = Is_global_interrupt_enabled())) Disable_global_interrupt();
Host_disable_sof_interrupt();
(void)Is_host_sof_interrupt_enabled();
if (sav_glob_int_en) Enable_global_interrupt();
}
return status;
}
