コード例 #1
0
ファイル: LcdDrv.c プロジェクト: tjusyj/FRDMKL46Z
/*
 LCD module initialization according to LCDConfig.h
 it is used as default configuration of the LCD 
 */
void vfnLCD_Init(void) {

     // enable IRCLK
     /*Enable IRCLK LCD source and disconnect from FLL by clearing IREFS */
     MCG_C1= 0x02;
     
     SIM_SCGC5 |= SIM_SCGC5_SLCD_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
     
     // Enable IRCLK 
     MCG_C1 |= MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK;
     MCG_C2 |= !MCG_C2_IRCS_MASK ;  //0 32KHZ internal reference clock; 1= 4MHz irc

     
       
     //vfnLCD_interrupt_init();       
     
     LCD_GCR = 0x0;
     LCD_AR  = 0x0;

 //    lcd_pinmux(0); 
     
/* LCD configurartion according to */     
      LCD_GCR =  (  LCD_GCR_RVEN_MASK*_LCDRVEN  
                   | LCD_GCR_RVTRIM(_LCDRVTRIM)    //0-15
                   | LCD_GCR_CPSEL_MASK*_LCDCPSEL 
                 /*  | LCD_GCR_HREFSEL_MASK*_LCDHREF  */
                    |LCD_GCR_LADJ(_LCDLOADADJUST)     //0-3*/
                 /*  | LCD_GCR_VSUPPLY(_LCDSUPPLY)  //0-3*/
                  /* |!LCD_GCR_LCDIEN_MASK */
                   |!LCD_GCR_FDCIEN_MASK
                   | LCD_GCR_ALTDIV(_LCDALTDIV)  //0-3
               /*    |!LCD_GCR_LCDWAIT_MASK  */
                   |!LCD_GCR_LCDSTP_MASK
                   |!LCD_GCR_LCDEN_MASK 
                   | LCD_GCR_SOURCE_MASK*_LCDCLKSOURCE
                   | LCD_GCR_ALTSOURCE_MASK*_LCDALRCLKSOURCE  
                   | LCD_GCR_LCLK(_LCDLCK)   //0-7
                   | LCD_GCR_DUTY(_LCDDUTY)   //0-7
                 );    
     
      lcd_alternate_mode = LCD_NORMAL_MODE;          //Message will be written to default backplanes  if = 4
     
      vfnLCD_EnablePins();         // Enable LCD pins and **Configure BackPlanes**
      
      LCD_GCR |= LCD_GCR_LCDEN_MASK;
   /*   LCD_GCR |= LCD_GCR_LCDIEN_MASK;    // Enable interrupts */
      
      
   /* Configure LCD Auxiliar Register*/   
      LCD_AR  = LCD_AR_BRATE(_LCDBLINKRATE); // all other flags set as zero
      vfnLCD_Write_Msg("1235");

}
コード例 #2
0
ファイル: LCD.c プロジェクト: Lyanzh/Learning_Material
void vfnLCD_Init(void)
{

   

     SIM_SCGC5 |= SIM_SCGC5_SLCD_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
     
     //* configure pins for LCD operation    
  PORTC_PCR20 = 0x00000000;     //VLL2
  PORTC_PCR21 = 0x00000000;     //VLL1
  PORTC_PCR22 = 0x00000000;     //VCAP2
  PORTC_PCR23 = 0x00000000;     //VCAP1

     
     
     // Enable IRCLK 
     MCG_C1  = MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK;
     MCG_C2 &= ~MCG_C2_IRCS_MASK ;  //0 32KHZ internal reference clock; 1= 4MHz irc


     vfnLCD_interrupt_init();       
     
     LCD_GCR = 0x0;
     LCD_AR  = 0x0;

 //    lcd_pinmux(0); 
     
/* LCD configurartion according to */     
      LCD_GCR =  (   LCD_GCR_RVEN_MASK*_LCDRVEN  
                   | LCD_GCR_RVTRIM(_LCDRVTRIM)    //0-15
                   | LCD_GCR_CPSEL_MASK*_LCDCPSEL 
                   | LCD_GCR_LADJ(_LCDLOADADJUST)     //0-3*/
                   | LCD_GCR_VSUPPLY_MASK*_LCDSUPPLY  //0-1*/
                   |!LCD_GCR_FDCIEN_MASK
                   | LCD_GCR_ALTDIV(_LCDALTDIV)  //0-3
                   |!LCD_GCR_LCDDOZE_MASK  
                   |!LCD_GCR_LCDSTP_MASK
                   |!LCD_GCR_LCDEN_MASK    //WILL BE ENABLE ON SUBSEQUENT STEP
                   | LCD_GCR_SOURCE_MASK*_LCDCLKSOURCE
                   | LCD_GCR_ALTSOURCE_MASK*_LCDALRCLKSOURCE  
                   | LCD_GCR_LCLK(_LCDLCK)   //0-7
                   | LCD_GCR_DUTY(_LCDDUTY)   //0-7
                 );    
     
      lcd_alternate_mode = LCD_NORMAL_MODE;          //Message will be written to default backplanes  if = 4
     
      vfnEnablePins();         // Enable LCD pins and Configure BackPlanes
 
      
      LCD_GCR |= LCD_GCR_LCDEN_MASK;
   /*   LCD_GCR |= LCD_GCR_LCDIEN_MASK;    // Enable interrupts */
      
      
   /* Configure LCD Auxiliar Register*/   
      LCD_AR  = LCD_AR_BRATE(_LCDBLINKRATE); // all other flags set as zero
     // print_slcd_registers();
      
     
      
     
  }
コード例 #3
0
/**
  void _LCDModule_Init(void)
  Parameters: None
  Description: This functions configures the registers of the SLCD Module
*/
void _SLCDModule_Init(void)
{
  MCG_C1 |= MCG_C1_IRCLKEN_MASK;
  //enable clock gate for Ports
  SIM_SCGC5 |=  ( !SIM_SCGC5_LPTIMER_MASK
                | !SIM_SCGC5_REGFILE_MASK
                | !SIM_SCGC5_TSI_MASK
                | SIM_SCGC5_PORTB_MASK
                | SIM_SCGC5_PORTC_MASK
                | SIM_SCGC5_PORTD_MASK
                );
  // Master General Purpose Control Register - Set mux to LCD analog operation.
  // After RESET these register are configured as 0 but indicated here for reference
  PORTB_PCR1  = PORT_PCR_MUX(0); //LCD_P1 
  PORTB_PCR2  = PORT_PCR_MUX(0); //LCD_P2
  PORTB_PCR3  = PORT_PCR_MUX(0); //LCD_P3
  PORTB_PCR4  = PORT_PCR_MUX(0); //LCD_P4
  PORTB_PCR5  = PORT_PCR_MUX(0); //LCD_P5
  PORTB_PCR6  = PORT_PCR_MUX(0); //LCD_P6
  PORTB_PCR7  = PORT_PCR_MUX(0); //LCD_P7
  PORTB_PCR8  = PORT_PCR_MUX(0); //LCD_P8
  PORTB_PCR9  = PORT_PCR_MUX(0); //LCD_P9
  PORTB_PCR10 = PORT_PCR_MUX(0); //LCD_P10
  PORTB_PCR11 = PORT_PCR_MUX(0); //LCD_P11
  PORTB_PCR16 = PORT_PCR_MUX(0); //LCD_P12
  PORTB_PCR17 = PORT_PCR_MUX(0); //LCD_P13
  PORTB_PCR18 = PORT_PCR_MUX(0); //LCD_P14
  PORTB_PCR19 = PORT_PCR_MUX(0); //LCD_P15
  PORTB_PCR20 = PORT_PCR_MUX(0); //LCD_P16
  PORTB_PCR21 = PORT_PCR_MUX(0); //LCD_P17
  PORTB_PCR22 = PORT_PCR_MUX(0); //LCD_P18
  PORTB_PCR23 = PORT_PCR_MUX(0); //LCD_P19
  PORTC_PCR0  = PORT_PCR_MUX(0); //LCD_P20
  PORTC_PCR1  = PORT_PCR_MUX(0); //LCD_P21
  PORTC_PCR2  = PORT_PCR_MUX(0); //LCD_P22
  PORTC_PCR3  = PORT_PCR_MUX(0); //LCD_P23
  PORTC_PCR4  = PORT_PCR_MUX(0); //LCD_P24
  PORTC_PCR5  = PORT_PCR_MUX(0); //LCD_P25
  PORTC_PCR6  = PORT_PCR_MUX(0); //LCD_P26
  PORTC_PCR7  = PORT_PCR_MUX(0); //LCD_P27
  PORTC_PCR8  = PORT_PCR_MUX(0); //LCD_P28
  PORTC_PCR9  = PORT_PCR_MUX(0); //LCD_P29
  PORTC_PCR10 = PORT_PCR_MUX(0); //LCD_P30
  PORTC_PCR11 = PORT_PCR_MUX(0); //LCD_P31
  PORTC_PCR12 = PORT_PCR_MUX(0); //LCD_P32
  PORTC_PCR13 = PORT_PCR_MUX(0); //LCD_P33
  PORTC_PCR14 = PORT_PCR_MUX(0); //LCD_P34
  PORTC_PCR15 = PORT_PCR_MUX(0); //LCD_P35
  PORTC_PCR16 = PORT_PCR_MUX(0); //LCD_P36
  PORTC_PCR17 = PORT_PCR_MUX(0); //LCD_P37
  PORTC_PCR18 = PORT_PCR_MUX(0); //LCD_P38
  PORTC_PCR19 = PORT_PCR_MUX(0); //LCD_P39  
  PORTD_PCR0  = PORT_PCR_MUX(0); //LCD_P40
  PORTD_PCR1  = PORT_PCR_MUX(0); //LCD_P41
  PORTD_PCR2  = PORT_PCR_MUX(0); //LCD_P42  
  PORTD_PCR3  = PORT_PCR_MUX(0); //LCD_P43  
  PORTD_PCR4  = PORT_PCR_MUX(0); //LCD_P44
  PORTD_PCR5  = PORT_PCR_MUX(0); //LCD_P45  
  PORTD_PCR6  = PORT_PCR_MUX(0); //LCD_P46  
  PORTD_PCR7  = PORT_PCR_MUX(0); //LCD_P47  
  
  // Configure NVIC for SLCD interrupt SLCD interrupt vector = 102
  // NVICICPR2 |= (1<<22); //Clear any pending interrupts on LCD
  // NVICISER2 |= (1<<22); //Enable interrupts from LCD interrupt*/
  // SLCD clock gate on
  SIM_SCGC3 |= SIM_SCGC3_SLCD_MASK;
  
  // Disable LCD
  LCD_GCR = 0;

  // Enable LCD pins 1-47
  LCD_PENH = 0;
  LCD_PENH = 0x0000FFFF;
  LCD_PENL = 0;
  LCD_PENL = 0xFFFFFFFE;
  // Enable LCD pins used as Backplanes 0-7
  LCD_BPENH = 0;
  LCD_BPENH = 0x0000FF00;
  LCD_BPENL = 0;
  // Configure backplane phase
  LCD_WF43TO40 = 0x08040201;
  LCD_WF47TO44 = 0x80402010;
  // Fill information on what segments are going to be turned on. Front Plane information
  LCD_WF3TO0   = 0;
  LCD_WF7TO4   = 0;
  LCD_WF11TO8  = 0;
  LCD_WF15TO12 = 0;  
  LCD_WF19TO16 = 0;
  LCD_WF23TO20 = 0;
  LCD_WF27TO24 = 0;
  LCD_WF31TO28 = 0;
  LCD_WF35TO32 = 0;
  LCD_WF39TO36 = 0;
  
  // Configure LCD Control Register
  LCD_GCR |=  ( LCD_GCR_CPSEL_MASK
              | LCD_GCR_RVEN_MASK
              | LCD_GCR_RVTRIM(15)
              | !LCD_GCR_HREFSEL_MASK // ( 0 - 3 Volts LCDs / 1 - 5 Volts LCDs)
              | LCD_GCR_LADJ(3) //0-3
              | LCD_GCR_VSUPPLY(3) //0-3
              | !LCD_GCR_LCDIEN_MASK
              | !LCD_GCR_FDCIEN_MASK
              | LCD_GCR_ALTDIV(1) //0-3
              | !LCD_GCR_LCDWAIT_MASK
              | !LCD_GCR_LCDSTP_MASK
              | !LCD_GCR_LCDEN_MASK
              | LCD_GCR_SOURCE_MASK
              | LCD_GCR_LCLK(0) //0-3
              | LCD_GCR_DUTY(7) //0-7
              );
  // Enable LCD module
  LCD_GCR |= LCD_GCR_LCDEN_MASK; 
}