void serial_setbrg (void)
{
unsigned int quot = 0;
int uart = CONFIG_SYS_IXP425_CONSOLE;
if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0))
quot = SERIAL_CLOCK / gd->baudrate;
else
hang ();
IER(uart) = 0; /* Disable for now */
FCR(uart) = 0; /* No fifos enabled */
/* set baud rate */
LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
DLL(uart) = quot & 0xff;
DLH(uart) = quot >> 8;
LCR(uart) = LCR_WLS0 | LCR_WLS1;
#ifdef CONFIG_SERIAL_RTS_ACTIVE
MCR(uart) = MCR_RTS; /* set RTS active */
#else
MCR(uart) = 0; /* set RTS inactive */
#endif
IER(uart) = IER_UUE;
}
static void uart_init_line(int port, unsigned long baud)
{
int i, baudconst;
switch (baud) {
case 115200:
baudconst = 1;
break;
case 57600:
baudconst = 2;
break;
case 38400:
baudconst = 3;
break;
case 19200:
baudconst = 6;
break;
case 9600:
default:
baudconst = 12;
break;
}
outb(0x87, LCR(port));
outb(0x00, DLM(port));
outb(baudconst, DLL(port));
outb(0x07, LCR(port));
outb(0x0f, MCR(port));
for (i = 10; i > 0; i--) {
if (inb(LSR(port)) == (unsigned int) 0)
break;
inb(RBR(port));
}
}
static void fpga_reset(int iobase)
{
outb(0, IER(iobase));
outb(LCR_DLAB | LCR_BIT5, LCR(iobase));
outb(1, DLL(iobase));
outb(0, DLM(iobase));
outb(LCR_BIT5, LCR(iobase));
inb(LSR(iobase));
inb(MSR(iobase));
/* turn off FPGA supply voltage */
outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));
delay(100);
/* turn on FPGA supply voltage again */
outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));
delay(100);
}
static inline void ser12_set_divisor(struct net_device *dev,
unsigned char divisor)
{
outb(0x81, LCR(dev->base_addr)); /* DLAB = 1 */
outb(divisor, DLL(dev->base_addr));
outb(0, DLM(dev->base_addr));
outb(0x01, LCR(dev->base_addr)); /* word length = 6 */
/*
* make sure the next interrupt is generated;
* 0 must be used to power the modem; the modem draws its
* power from the TxD line
*/
outb(0x00, THR(dev->base_addr));
/*
* it is important not to set the divider while transmitting;
* this reportedly makes some UARTs generating interrupts
* in the hundredthousands per second region
* Reported by: [email protected] (Ignacio Arenaza Nuno)
*/
}
Rank max_in_3(T* arr, Rank p, Rank end) {
Rank l = LCR(p), r = RCR(p);
if (r < end) {
return arr[p] >= arr[l] ? (arr[p] >= arr[r] ? p : r) : (arr[l] >= arr[r] ? l : r);
}
else if (l < end) {
return arr[p] >= arr[l] ? p : l;
}
else {
return p;
}
}
static void yam_set_uart(struct net_device *dev)
{
struct yam_port *yp = netdev_priv(dev);
int divisor = 115200 / yp->baudrate;
outb(0, IER(dev->base_addr));
outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr));
outb(divisor, DLL(dev->base_addr));
outb(0, DLM(dev->base_addr));
outb(LCR_BIT8, LCR(dev->base_addr));
outb(PTT_OFF, MCR(dev->base_addr));
outb(0x00, FCR(dev->base_addr));
/* Flush pending irq */
inb(RBR(dev->base_addr));
inb(MSR(dev->base_addr));
/* Enable rx irq */
outb(ENABLE_RTXINT, IER(dev->base_addr));
}
static void set_baud_rate(struct device *dev, u32_t baud_rate)
{
const struct uart_ns16550_device_config * const dev_cfg = DEV_CFG(dev);
struct uart_ns16550_dev_data_t * const dev_data = DEV_DATA(dev);
u32_t divisor; /* baud rate divisor */
u8_t lcr_cache;
if ((baud_rate != 0) && (dev_cfg->sys_clk_freq != 0)) {
/* calculate baud rate divisor */
divisor = (dev_cfg->sys_clk_freq / baud_rate) >> 4;
/* set the DLAB to access the baud rate divisor registers */
lcr_cache = INBYTE(LCR(dev));
OUTBYTE(LCR(dev), LCR_DLAB | lcr_cache);
OUTBYTE(BRDL(dev), (unsigned char)(divisor & 0xff));
OUTBYTE(BRDH(dev), (unsigned char)((divisor >> 8) & 0xff));
/* restore the DLAB to access the baud rate divisor registers */
OUTBYTE(LCR(dev), lcr_cache);
dev_data->baud_rate = baud_rate;
}