/** * @brief De-initialize the DMA registers to their default reset values. * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: * @arg @ref LL_DMA_STREAM_0 * @arg @ref LL_DMA_STREAM_1 * @arg @ref LL_DMA_STREAM_2 * @arg @ref LL_DMA_STREAM_3 * @arg @ref LL_DMA_STREAM_4 * @arg @ref LL_DMA_STREAM_5 * @arg @ref LL_DMA_STREAM_6 * @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_ALL * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA registers are de-initialized * - ERROR: DMA registers are not de-initialized */ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream) { DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0; ErrorStatus status = SUCCESS; /* Check the DMA Instance DMAx and Stream parameters*/ assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); if (Stream == LL_DMA_STREAM_ALL) { if (DMAx == DMA1) { /* Force reset of DMA clock */ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); /* Release reset of DMA clock */ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); } else if (DMAx == DMA2) { /* Force reset of DMA clock */ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); /* Release reset of DMA clock */ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); } else { status = ERROR; } } else { /* Disable the selected Stream */ LL_DMA_DisableStream(DMAx,Stream); /* Get the DMA Stream Instance */ tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream)); /* Reset DMAx_Streamy configuration register */ LL_DMA_WriteReg(tmp, CR, 0U); /* Reset DMAx_Streamy remaining bytes register */ LL_DMA_WriteReg(tmp, NDTR, 0U); /* Reset DMAx_Streamy peripheral address register */ LL_DMA_WriteReg(tmp, PAR, 0U); /* Reset DMAx_Streamy memory address register */ LL_DMA_WriteReg(tmp, M0AR, 0U); /* Reset DMAx_Streamy memory address register */ LL_DMA_WriteReg(tmp, M1AR, 0U); /* Reset DMAx_Streamy FIFO control register */ LL_DMA_WriteReg(tmp, FCR, 0x00000021U); /* Reset Channel register field for DMAx Stream*/ LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0); if(Stream == LL_DMA_STREAM_0) { /* Reset the Stream0 pending flags */ DMAx->LIFCR = 0x0000003FU; } else if(Stream == LL_DMA_STREAM_1) { /* Reset the Stream1 pending flags */ DMAx->LIFCR = 0x00000F40U; } else if(Stream == LL_DMA_STREAM_2) { /* Reset the Stream2 pending flags */ DMAx->LIFCR = 0x003F0000U; } else if(Stream == LL_DMA_STREAM_3) { /* Reset the Stream3 pending flags */ DMAx->LIFCR = 0x0F400000U; } else if(Stream == LL_DMA_STREAM_4) { /* Reset the Stream4 pending flags */ DMAx->HIFCR = 0x0000003FU; } else if(Stream == LL_DMA_STREAM_5) { /* Reset the Stream5 pending flags */ DMAx->HIFCR = 0x00000F40U; } else if(Stream == LL_DMA_STREAM_6) { /* Reset the Stream6 pending flags */ DMAx->HIFCR = 0x003F0000U; } else if(Stream == LL_DMA_STREAM_7) { /* Reset the Stream7 pending flags */ DMAx->HIFCR = 0x0F400000U; } else { status = ERROR; } } return status; }
/** * @brief De-initialize the DMA registers to their default reset values. * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @arg @ref LL_DMA_CHANNEL_ALL * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA registers are de-initialized * - ERROR: DMA registers are not de-initialized */ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) { DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; ErrorStatus status = SUCCESS; /* Check the DMA Instance DMAx and Channel parameters*/ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL)); if (Channel == LL_DMA_CHANNEL_ALL) { if (DMAx == DMA1) { /* Force reset of DMA clock */ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); /* Release reset of DMA clock */ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); } #if defined(DMA2) else if (DMAx == DMA2) { /* Force reset of DMA clock */ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); /* Release reset of DMA clock */ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); } #endif else { status = ERROR; } } else { tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); /* Disable the selected DMAx_Channely */ CLEAR_BIT(tmp->CCR, DMA_CCR_EN); /* Reset DMAx_Channely control register */ LL_DMA_WriteReg(tmp, CCR, 0U); /* Reset DMAx_Channely remaining bytes register */ LL_DMA_WriteReg(tmp, CNDTR, 0U); /* Reset DMAx_Channely peripheral address register */ LL_DMA_WriteReg(tmp, CPAR, 0U); /* Reset DMAx_Channely memory address register */ LL_DMA_WriteReg(tmp, CMAR, 0U); /* Reset Request register field for DMAx Channel */ LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0); if (Channel == LL_DMA_CHANNEL_1) { /* Reset interrupt pending bits for DMAx Channel1 */ LL_DMA_ClearFlag_GI1(DMAx); } else if (Channel == LL_DMA_CHANNEL_2) { /* Reset interrupt pending bits for DMAx Channel2 */ LL_DMA_ClearFlag_GI2(DMAx); } else if (Channel == LL_DMA_CHANNEL_3) { /* Reset interrupt pending bits for DMAx Channel3 */ LL_DMA_ClearFlag_GI3(DMAx); } else if (Channel == LL_DMA_CHANNEL_4) { /* Reset interrupt pending bits for DMAx Channel4 */ LL_DMA_ClearFlag_GI4(DMAx); } else if (Channel == LL_DMA_CHANNEL_5) { /* Reset interrupt pending bits for DMAx Channel5 */ LL_DMA_ClearFlag_GI5(DMAx); } else if (Channel == LL_DMA_CHANNEL_6) { /* Reset interrupt pending bits for DMAx Channel6 */ LL_DMA_ClearFlag_GI6(DMAx); } else if (Channel == LL_DMA_CHANNEL_7) { /* Reset interrupt pending bits for DMAx Channel7 */ LL_DMA_ClearFlag_GI7(DMAx); } else { status = ERROR; } } return status; }
/** * @brief De-initialize the DMA registers to their default reset values. * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA registers are de-initialized * - ERROR: DMA registers are not de-initialized */ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) { DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; ErrorStatus status = SUCCESS; /* Check the DMA Instance DMAx and Channel parameters*/ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); /* Disable the selected DMAx_Channely */ CLEAR_BIT(tmp->CCR, DMA_CCR_EN); /* Reset DMAx_Channely control register */ LL_DMA_WriteReg(tmp, CCR, 0U); /* Reset DMAx_Channely remaining bytes register */ LL_DMA_WriteReg(tmp, CNDTR, 0U); /* Reset DMAx_Channely peripheral address register */ LL_DMA_WriteReg(tmp, CPAR, 0U); /* Reset DMAx_Channely memory address register */ LL_DMA_WriteReg(tmp, CMAR, 0U); if (Channel == LL_DMA_CHANNEL_1) { /* Reset interrupt pending bits for DMAx Channel1 */ LL_DMA_ClearFlag_GI1(DMAx); } else if (Channel == LL_DMA_CHANNEL_2) { /* Reset interrupt pending bits for DMAx Channel2 */ LL_DMA_ClearFlag_GI2(DMAx); } else if (Channel == LL_DMA_CHANNEL_3) { /* Reset interrupt pending bits for DMAx Channel3 */ LL_DMA_ClearFlag_GI3(DMAx); } else if (Channel == LL_DMA_CHANNEL_4) { /* Reset interrupt pending bits for DMAx Channel4 */ LL_DMA_ClearFlag_GI4(DMAx); } else if (Channel == LL_DMA_CHANNEL_5) { /* Reset interrupt pending bits for DMAx Channel5 */ LL_DMA_ClearFlag_GI5(DMAx); } else if (Channel == LL_DMA_CHANNEL_6) { /* Reset interrupt pending bits for DMAx Channel6 */ LL_DMA_ClearFlag_GI6(DMAx); } else if (Channel == LL_DMA_CHANNEL_7) { /* Reset interrupt pending bits for DMAx Channel7 */ LL_DMA_ClearFlag_GI7(DMAx); } else { status = ERROR; } return status; }