/** * @brief Return PLL clock frequency used for system domain * @retval PLL clock frequency (in Hz) */ uint32_t RCC_PLL_GetFreqDomain_SYS(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllsource = LL_RCC_PLL_GetMainSource(); switch (pllsource) { case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE; break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllinputfreq = HSE_VALUE; break; default: pllinputfreq = HSI_VALUE; break; } return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); }
/** * @brief Return PLL clock frequency used for SAI domain * @retval PLL clock frequency (in Hz) */ uint32_t RCC_PLL_GetFreqDomain_SAI(void) { uint32_t pllinputfreq = 0, pllsource = 0; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN SAI Domain clock = PLL_VCO / PLLP */ pllsource = LL_RCC_PLL_GetMainSource(); switch (pllsource) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), (LL_RCC_MSI_IsEnabledRangeSelect() ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE; break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllinputfreq = HSE_VALUE; break; default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), (LL_RCC_MSI_IsEnabledRangeSelect() ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; } return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); }