void clock_config(void)
{
LL_RCC_HSE_Enable();
while (!LL_RCC_HSE_IsReady());
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLL_MUL_9);
LL_RCC_PLL_Disable();
LL_RCC_PLL_Enable();
while (!LL_RCC_PLL_IsReady());
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSRC_PCLK2_DIV_4);
LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
LL_FLASH_EnablePrefetch();
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
SystemCoreClockUpdate();
LL_Init1msTick(SystemCoreClock);
}
static int stm32_clock_control_init(struct device *dev)
{
LL_UTILS_ClkInitTypeDef s_ClkInitStruct;
ARG_UNUSED(dev);
/* configure clock for AHB/APB buses */
config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct);
/* Some clocks would be activated by default */
config_enable_default_clocks();
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
LL_UTILS_PLLInitTypeDef s_PLLInitStruct;
/* configure PLL input settings */
config_pll_init(&s_PLLInitStruct);
/*
* Switch to HSI and disable the PLL before configuration.
* (Switching to HSI makes sure we have a SYSCLK source in
* case we're currently running from the PLL we're about to
* turn off and reconfigure.)
*
* Don't use s_ClkInitStruct.AHBCLKDivider as the AHB
* prescaler here. In this configuration, that's the value to
* use when the SYSCLK source is the PLL, not HSI.
*/
stm32_clock_switch_to_hsi(LL_RCC_SYSCLK_DIV_1);
LL_RCC_PLL_Disable();
#ifdef CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ,
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
<< POSITION_VAL(RCC_PLLCFGR_PLLQ));
#endif /* CONFIG_CLOCK_STM32_PLL_Q_DIVISOR */
#ifdef CONFIG_CLOCK_STM32_PLL_SRC_MSI
/* Switch to PLL with MSI as clock source */
LL_PLL_ConfigSystemClock_MSI(&s_PLLInitStruct, &s_ClkInitStruct);
/* Disable other clocks */
LL_RCC_HSI_Disable();
LL_RCC_HSE_Disable();
#elif CONFIG_CLOCK_STM32_PLL_SRC_HSI
/* Switch to PLL with HSI as clock source */
LL_PLL_ConfigSystemClock_HSI(&s_PLLInitStruct, &s_ClkInitStruct);
/* Disable other clocks */
LL_RCC_HSE_Disable();
LL_RCC_MSI_Disable();
#elif CONFIG_CLOCK_STM32_PLL_SRC_HSE
int hse_bypass = LL_UTILS_HSEBYPASS_OFF;
#ifdef CONFIG_CLOCK_STM32_HSE_BYPASS
hse_bypass = LL_UTILS_HSEBYPASS_ON;
#endif /* CONFIG_CLOCK_STM32_HSE_BYPASS */
/* Switch to PLL with HSE as clock source */
LL_PLL_ConfigSystemClock_HSE(CONFIG_CLOCK_STM32_HSE_CLOCK, hse_bypass,
&s_PLLInitStruct,
&s_ClkInitStruct);
/* Disable other clocks */
LL_RCC_HSI_Disable();
LL_RCC_MSI_Disable();
#endif /* CONFIG_CLOCK_STM32_PLL_SRC_... */
#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE
/* Enable HSE if not enabled */
if (LL_RCC_HSE_IsReady() != 1) {
/* Check if need to enable HSE bypass feature or not */
#ifdef CONFIG_CLOCK_STM32_HSE_BYPASS
LL_RCC_HSE_EnableBypass();
#else
LL_RCC_HSE_DisableBypass();
#endif /* CONFIG_CLOCK_STM32_HSE_BYPASS */
/* Enable HSE */
LL_RCC_HSE_Enable();
while (LL_RCC_HSE_IsReady() != 1) {
/* Wait for HSE ready */
}
}
/* Set HSE as SYSCLCK source */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
LL_RCC_SetAHBPrescaler(s_ClkInitStruct.AHBCLKDivider);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
}
/* Update SystemCoreClock variable */
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(
CONFIG_CLOCK_STM32_HSE_CLOCK,
s_ClkInitStruct.AHBCLKDivider));
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
#ifndef CONFIG_SOC_SERIES_STM32F0X
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
#endif /* CONFIG_SOC_SERIES_STM32F0X */
/* Set flash latency */
/* HSI used as SYSCLK, set latency to 0 */
LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
/* Disable other clocks */
LL_RCC_HSI_Disable();
LL_RCC_MSI_Disable();
LL_RCC_PLL_Disable();
#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI
stm32_clock_switch_to_hsi(s_ClkInitStruct.AHBCLKDivider);
/* Update SystemCoreClock variable */
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(HSI_VALUE,
s_ClkInitStruct.AHBCLKDivider));
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
#ifndef CONFIG_SOC_SERIES_STM32F0X
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
#endif /* CONFIG_SOC_SERIES_STM32F0X */
/* Set flash latency */
/* HSI used as SYSCLK, set latency to 0 */
LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
/* Disable other clocks */
LL_RCC_HSE_Disable();
LL_RCC_MSI_Disable();
LL_RCC_PLL_Disable();
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_... */
return 0;
}
