/** * @brief Configure the encoder interface of the timer instance. * @param TIMx Timer Instance * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { uint32_t tmpccmr1 = 0U; uint32_t tmpccer = 0U; /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); /* Get the TIMx CCMR1 register value */ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Configure TI1 */ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); /* Configure TI2 */ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); /* Set encoder mode */ LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); /* Write to TIMx CCMR1 */ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; }
/** * @brief Configure the TIMx output channel 5. * @param TIMx Timer Instance * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3 = 0U; uint32_t tmpccer = 0U; /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 5: Reset the CC5E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx CCMR3 register value */ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); /* Select the Output Compare Mode */ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); /* Set the Output Compare Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the Output Idle state */ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); } /* Write to TIMx CCMR3 */ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); /* Set the Capture Compare Register value */ LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; }
/** * @brief Configure the TIMx output channel 4. * @param TIMx Timer Instance * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2 = 0U; uint32_t tmpccer = 0U; uint32_t tmpcr2 = 0U; /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx CR2 register value */ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); /* Get the TIMx CCMR2 register value */ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); /* Reset Capture/Compare selection Bits */ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); /* Select the Output Compare Mode */ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); /* Set the Output Compare Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); /* Write to TIMx CCMR2 */ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); /* Set the Capture Compare Register value */ LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; }
/** * @brief Configure the TIMx time base unit. * @param TIMx Timer Instance * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) { uint32_t tmpcr1 = 0U; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(TIMx)); assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) { /* Select the Counter Mode */ MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); } /* Write to TIMx CR1 */ LL_TIM_WriteReg(TIMx, CR1, tmpcr1); /* Set the Autoreload value */ LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); /* Set the Prescaler value */ LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) { /* Set the Repetition Counter value */ LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); } /* Generate an update event to reload the Prescaler and the repetition counter value (if applicable) immediately */ LL_TIM_GenerateEvent_UPDATE(TIMx); return SUCCESS; }
/** * @brief Configure the TIMx output channel 3. * @param TIMx Timer Instance * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2 = 0U; uint32_t tmpccer = 0U; uint32_t tmpcr2 = 0U; /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx CR2 register value */ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); /* Get the TIMx CCMR2 register value */ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); /* Reset Capture/Compare selection Bits */ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); /* Select the Output Compare Mode */ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); /* Set the Output Compare Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); /* Set the complementary output State */ MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); /* Set the Output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); /* Set the complementary output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); } /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); /* Write to TIMx CCMR2 */ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); /* Set the Capture Compare Register value */ LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; }
/** * @brief Configure the Hall sensor interface of the timer instance. * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR * to the TI1 input channel * @note TIMx slave mode controller is configured in reset mode. Selected internal trigger is TI1F_ED. * @note Channel 1 is configured as input, IC1 is mapped on TRC. * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed * between 2 changes on the inputs. It gives information about motor speed. * @note Channel 2 is configured in output PWM 2 mode. * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. * @note OC2REF is selected as trigger output on TRGO. * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { uint32_t tmpcr2 = 0U; uint32_t tmpccmr1 = 0U; uint32_t tmpccer = 0U; uint32_t tmpsmcr = 0U; /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); /* Get the TIMx CR2 register value */ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); /* Get the TIMx CCMR1 register value */ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx SMCR register value */ tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ tmpcr2 |= TIM_CR2_TI1S; /* OC2REF signal is used as trigger output (TRGO) */ tmpcr2 |= LL_TIM_TRGO_OC2REF; /* Configure the slave mode controller */ tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); tmpsmcr |= LL_TIM_TS_TI1F_ED; tmpsmcr |= LL_TIM_SLAVEMODE_RESET; /* Configure input channel 1 */ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); /* Configure input channel 2 */ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); /* Write to TIMx SMCR */ LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); /* Write to TIMx CCMR1 */ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); /* Write to TIMx CCR2 */ LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); return SUCCESS; }