static void gen2_emit_copy_pipeline(struct intel_batchbuffer *batch)
{
OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
DISABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
LOAD_TEXTURE_BLEND_STAGE(0) | 1);
OUT_BATCH(TB0C_LAST_STAGE | TB0C_RESULT_SCALE_1X |
TB0C_OUTPUT_WRITE_CURRENT |
TB0C_OP_ARG1 | TB0C_ARG1_SEL_TEXEL0);
OUT_BATCH(TB0A_RESULT_SCALE_1X | TB0A_OUTPUT_WRITE_CURRENT |
TB0A_OP_ARG1 | TB0A_ARG1_SEL_TEXEL0);
}
static void i830_emit_composite_state(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
uint32_t vf2, tiling_bits;
uint32_t texcoordfmt = 0;
intel->needs_render_state_emit = FALSE;
IntelEmitInvarientState(scrn);
intel->last_3d = LAST_3D_RENDER;
assert(intel->in_batch_atomic);
if (intel_pixmap_tiled(intel->render_dest)) {
tiling_bits = BUF_3D_TILED_SURFACE;
if (intel_get_pixmap_private(intel->render_dest)->tiling
== I915_TILING_Y)
tiling_bits |= BUF_3D_TILE_WALK_Y;
} else
tiling_bits = 0;
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
BUF_3D_PITCH(intel_pixmap_pitch(intel->render_dest)));
OUT_RELOC_PIXMAP(intel->render_dest,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
OUT_BATCH(intel->render_dest_format);
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
OUT_BATCH(0);
OUT_BATCH(0); /* ymin, xmin */
OUT_BATCH(DRAW_YMAX(intel->render_dest->drawable.height - 1) |
DRAW_XMAX(intel->render_dest->drawable.width - 1));
OUT_BATCH(0); /* yorig, xorig */
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
if (intel->render_mask)
vf2 = 2 << 12; /* 2 texture coord sets */
else
vf2 = 1 << 12;
OUT_BATCH(vf2); /* number of coordinate sets */
OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | intel->
s8_blendctl | S8_ENABLE_COLOR_BUFFER_WRITE);
OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
LOAD_TEXTURE_BLEND_STAGE(0) | 1);
OUT_BATCH(intel->cblend);
OUT_BATCH(intel->ablend);
OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
/* We have to explicitly say we don't want write disabled */
OUT_BATCH(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
DISABLE_DITHER | ENABLE_COLOR_WRITE | DISABLE_DEPTH_WRITE);
if (intel_transform_is_affine(intel->render_source_picture->transform))
texcoordfmt |= (TEXCOORDFMT_2D << 0);
else
texcoordfmt |= (TEXCOORDFMT_3D << 0);
if (intel->render_mask) {
if (intel_transform_is_affine
(intel->render_mask_picture->transform))
texcoordfmt |= (TEXCOORDFMT_2D << 2);
else
texcoordfmt |= (TEXCOORDFMT_3D << 2);
}
OUT_BATCH(_3DSTATE_VERTEX_FORMAT_2_CMD | texcoordfmt);
i830_texture_setup(intel->render_source_picture, intel->render_source, 0);
if (intel->render_mask) {
i830_texture_setup(intel->render_mask_picture,
intel->render_mask, 1);
}
}
