void halAudioGenerator_HbrClockDivider(IM_UINT16 baseAddress, IM_UINT16 value) { LOG_TRACE1(value); /* 9-bit width */ access_CoreWriteByte((u8) (value), baseAddress + AG_HBR_CLKDIV0); access_CoreWrite(value >> 8, baseAddress + AG_HBR_CLKDIV1, 0, 1); }
int edid_GetSad(u16 baseAddr, unsigned int n, shortAudioDesc_t * sad) { LOG_TRACE1(n); if (n < edid_GetSadCount(baseAddr)) { *sad = edid_mSad[n]; return TRUE; } return FALSE; }
int edid_GetSvd(u16 baseAddr, unsigned int n, shortVideoDesc_t * svd) { LOG_TRACE1(n); if (n < edid_GetSvdCount(baseAddr)) { *svd = edid_mSvd[n]; return TRUE; } return FALSE; }
int edid_GetDtd(u16 baseAddr, unsigned int n, dtd_t * dtd) { LOG_TRACE1(n); if (n < edid_GetDtdCount(baseAddr)) { *dtd = edid_mDtd[n]; return TRUE; } return FALSE; }
void halVideoPacketizer_PixelRepetitionFactor(u16 baseAddr, u8 value) { LOG_TRACE1(value); /* desired factor */ access_CoreWrite(value, (baseAddr + VP_PR_CD), 0, 4); /* enable stuffing */ access_CoreWrite(1, (baseAddr + VP_STUFF), 0, 1); /* enable block */ access_CoreWrite((value > 1) ? 1 : 0, (baseAddr + VP_CONF), 4, 1); /* bypass block */ access_CoreWrite((value > 1) ? 0 : 1, (baseAddr + VP_CONF), 2, 1); }
void api_AvMute(int enable) { LOG_TRACE1(enable); if (enable == TRUE) { packets_AvMute(api_mBaseAddress, enable); hdcp_AvMute(api_mBaseAddress, enable); } else { hdcp_AvMute(api_mBaseAddress, enable); packets_AvMute(api_mBaseAddress, enable); } }
VOID Signal_Post( Signal *pThis ) { //SEM_postBinary(pThis->Handle); #ifdef ToFindExcpError //LOG_TRACE1("Inside signalpost pThis->Handle : 0x%x",pThis->Handle); if(CSL_chipReadDNUM ()==1) { NumSignal++; LOG_TRACE1("signal posting :%d ",NumSignal); } #endif Semaphore_post(pThis->Handle); #ifdef ToFindExcpError // LOG_TRACE0(" signal posted"); #endif }
void halAudioGenerator_UserLeft(IM_UINT16 baseAddress, IM_UINT8 bit, IM_UINT8 channelNo) { LOG_TRACE1(bit); switch (channelNo) { case 0: access_CoreWrite(bit, baseAddress + AG_SPDIF_CONF, 2, 1); break; case 1: access_CoreWrite(bit, baseAddress + AG_GPA_USERBIT, 0, 1); break; case 2: access_CoreWrite(bit, baseAddress + AG_GPA_USERBIT, 2, 1); break; case 3: access_CoreWrite(bit, baseAddress + AG_GPA_USERBIT, 4, 1); break; default: LOG_ERROR("wrong channel number"); break; } }
void halAudioGenerator_IecChannelLeft(IM_UINT16 baseAddress, IM_UINT8 value, IM_UINT8 channelNo) { LOG_TRACE1(value); switch (channelNo) { case 0: access_CoreWrite(value, baseAddress + AG_SPDIF_AUDSCHNLS3, 0, 4); break; case 1: access_CoreWrite(value, baseAddress + AG_GPA_CHNUM1, 0, 4); break; case 2: access_CoreWrite(value, baseAddress + AG_GPA_CHNUM2, 0, 4); break; case 3: access_CoreWrite(value, baseAddress + AG_GPA_CHNUM3, 0, 4); break; default: LOG_ERROR("wrong channel number"); break; } }
void halVideoPacketizer_OutputSelector(u16 baseAddr, u8 value) { LOG_TRACE1(value); if (value == 0) { /* pixel packing */ access_CoreWrite(0, (baseAddr + VP_CONF), 6, 1); /* enable pixel packing */ access_CoreWrite(1, (baseAddr + VP_CONF), 5, 1); access_CoreWrite(0, (baseAddr + VP_CONF), 3, 1); } else if (value == 1) { /* YCC422 */ access_CoreWrite(0, (baseAddr + VP_CONF), 6, 1); access_CoreWrite(0, (baseAddr + VP_CONF), 5, 1); /* enable YCC422 */ access_CoreWrite(1, (baseAddr + VP_CONF), 3, 1); } else if (value == 2 || value == 3) { /* bypass */ /* enable bypass */ access_CoreWrite(1, (baseAddr + VP_CONF), 6, 1); access_CoreWrite(0, (baseAddr + VP_CONF), 5, 1); access_CoreWrite(0, (baseAddr + VP_CONF), 3, 1); } else { LOG_ERROR2("wrong output option: ", value); return; } /* YCC422 stuffing */ access_CoreWrite(1, (baseAddr + VP_STUFF), 2, 1); /* pixel packing stuffing */ access_CoreWrite(1, (baseAddr + VP_STUFF), 1, 1); /* ouput selector */ access_CoreWrite(value, (baseAddr + VP_CONF), 0, 2); }
int api_Reinitialize(u16 address, u8 dataEnablePolarity, u16 sfrClock, u8 force) //cmd:auto argument: 0, 1, 2500, 0 { dataEnablePolarity = 1; api_mDataEnablePolarity = dataEnablePolarity; api_mHpd = FALSE; api_mSendGamutOk = FALSE; //????????????????? api_mSfrClock = sfrClock; // sfrClock,that are required for setting the low time of the SCL clock in each speed mode LOG_NOTICE("dwc_hdmi_tx_software_api_2.12"); LOG_NOTICE(__DATE__); LOG_TRACE1(dataEnablePolarity); /* reset error */ error_Set(NO_ERROR); api_mBaseAddress = address; if (!api_mutex_inited) { mutex_Initialize(&api_mMutex); api_mutex_inited = 1; } if ((api_mCurrentState < API_HPD) || (api_mCurrentState > API_EDID_READ)) { /* if EDID read do not re-read, if HPDetected, keep in same state * otherwise, set to INIT */ api_mCurrentState = API_INIT; } if (system_InterruptHandlerRegister(TX_INT, api_EventHandler, NULL) == TRUE) { printk("==>enable TX_INT in %s:%d\n", __func__, __LINE__); //return system_InterruptEnable(TX_INT); printk("enter %s, %d\n", __func__, __LINE__); return TRUE; } return FALSE; }
void halFrameComposerAudio_PacketLayout(u16 baseAddr, u8 bit) { LOG_TRACE1(bit); access_CoreWrite(bit, baseAddr + FC_AUDSCONF, 0, 1); }
void halFrameComposerAudio_IecCgmsA(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWrite(value, baseAddr + FC_AUDSCHNLS0, 4, 2); }
void halFrameComposerAudio_IecWordLength(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWrite(value, baseAddr + FC_AUDSCHNLS8, 0, 4); }
void halFrameComposerAudio_PacketSampleFlat(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWrite(value, baseAddr + FC_AUDSCONF, 4, 4); }
void halFrameComposerAudio_IecClockAccuracy(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWrite(value, baseAddr + FC_AUDSCHNLS7, 4, 2); }
void halFrameComposerAudio_IecOriginalSamplingFreq(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWrite(value, baseAddr + FC_AUDSCHNLS8, 4, 4); }
void halFrameComposerGcp_DefaultPhase(u16 baseAddr, u8 uniform) { LOG_TRACE1(uniform); access_CoreWrite((uniform ? 1 : 0), (baseAddr + FC_GCP), DEFAULT_PHASE, 1); }
int api_HdcpBypassEncryption(int bypass) { LOG_TRACE1(bypass); hdcp_BypassEncryption(api_mBaseAddress, bypass); return TRUE; }
void halInterrupt_PacketsOverflowClear(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWriteByte(value, (baseAddr + IH_FC_STAT2)); }
void api_AudioMute(int enable) { LOG_TRACE1(enable); audio_Mute(api_mBaseAddress, enable); }
void halInterrupt_AudioSamplerClear(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWriteByte(value, (baseAddr + IH_AS_STAT0)); }
void halFrameComposerAudio_IecPcmMode(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWrite(value, baseAddr + FC_AUDSCHNLS2, 4, 3); }
int api_HdcpDisableEncryption(int disable) { LOG_TRACE1(disable); hdcp_DisableEncryption(api_mBaseAddress, disable); return TRUE; }
void halFrameComposerAudio_IecCopyright(u16 baseAddr, u8 bit) { LOG_TRACE1(bit); access_CoreWrite(bit, baseAddr + FC_AUDSCHNLS0, 0, 1); }
void halFrameComposerGcp_AvMute(u16 baseAddr, u8 enable) { LOG_TRACE1(enable); access_CoreWrite((enable ? 1 : 0), (baseAddr + FC_GCP), SET_AVMUTE, 1); access_CoreWrite((enable ? 0 : 1), (baseAddr + FC_GCP), CLEAR_AVMUTE, 1); }
void halFrameComposerAudio_IecCategoryCode(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWriteByte(value, baseAddr + FC_AUDSCHNLS1); }
void halInterrupt_I2cDdcClear(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWriteByte(value, (baseAddr + IH_I2CM_STAT0)); }
void halFrameComposerAudio_IecSource(u16 baseAddr, u8 value) { LOG_TRACE1(value); access_CoreWrite(value, baseAddr + FC_AUDSCHNLS2, 0, 4); }
int api_Initialize(u16 address, u8 dataEnablePolarity, u16 sfrClock, u8 force) //cmd:auto argument: 0, 1, 2500, 0 { dtd_t dtd; videoParams_t params; dataEnablePolarity = 1; api_mDataEnablePolarity = dataEnablePolarity; api_mHpd = FALSE; api_mSendGamutOk = FALSE; //????????????????? api_mSfrClock = sfrClock; // sfrClock,that are required for setting the low time of the SCL clock in each speed mode LOG_NOTICE("dwc_hdmi_tx_software_api_2.12"); LOG_NOTICE(__DATE__); LOG_TRACE1(dataEnablePolarity); /* reset error */ error_Set(NO_ERROR); api_mBaseAddress = address; if (!api_mutex_inited) { mutex_Initialize(&api_mMutex); api_mutex_inited = 1; } control_InterruptMute(api_mBaseAddress, ~0); /* disable all interrupts */ if ((api_mCurrentState < API_HPD) || (api_mCurrentState > API_EDID_READ)) { /* if EDID read do not re-read, if HPDetected, keep in same state * otherwise, NOT INIT */ api_mCurrentState = API_NOT_INIT; } /* VGA must be supported by all sinks * so use it as default configuration */ dtd_Fill(&dtd, 4, 60000); videoParams_Reset(¶ms); videoParams_SetHdmi(¶ms, TRUE); videoParams_SetDtd(¶ms, &dtd); /* params->mDtd = dtd; */ pixelClock = videoParams_GetPixelClock(¶ms); /* dtd_GetPixelClock(&(params->mDtd)); */ /* reset HAPS51 DEMO BOARD, by default mask all interrupts */ if (board_Initialize(api_mBaseAddress, pixelClock, 8) != TRUE) { return FALSE; } /* get Product Identification Register 0 */ LOG_NOTICE2("Product Line", control_ProductLine(api_mBaseAddress)); /* get Product Identification Register 1*/ LOG_NOTICE2("Product Type", control_ProductType(api_mBaseAddress)); /* if ((ProductLine == 0xA0) && ((ProductType == 0x01 || ProductType == 0xC1))) */ if (control_SupportsCore(api_mBaseAddress) != TRUE) { error_Set(ERR_HW_NOT_SUPPORTED); LOG_ERROR("Unknown device: aborting..."); return FALSE; } /* get Design Identification Register */ LOG_NOTICE2("HDMI TX Controller Design", control_Design(api_mBaseAddress)); /* get Revision Identification Register */ LOG_NOTICE2("HDMI TX Controller Revision", control_Revision(api_mBaseAddress)); /* if(ProductLine == 0xA0 && ProductType == 0xC1)*/ if (control_SupportsHdcp(api_mBaseAddress) == TRUE) { LOG_NOTICE("HDMI TX controller supports HDCP"); } /* print api_mDataEnablePolarity value ,always return TRUE */ if (video_Initialize(api_mBaseAddress, ¶ms, api_mDataEnablePolarity) != TRUE) { return FALSE; } if (audio_Initialize(api_mBaseAddress) != TRUE) { return FALSE; } if (packets_Initialize(api_mBaseAddress) != TRUE) { return FALSE; } if (hdcp_Initialize(api_mBaseAddress, api_mDataEnablePolarity) != TRUE) { return FALSE; } /* clock gate == 1 => turn off all modules */ if (control_Initialize(api_mBaseAddress, api_mDataEnablePolarity, pixelClock) != TRUE) { return FALSE; } #ifdef CONFIG_HMDI_JZ4780_DEBUG printk("jz4780 hdmi %s %d phy init\n",__func__,__LINE__); #endif control_InterruptClearAll(api_mBaseAddress); if (board_PixelClock(api_mBaseAddress, pixelClock, videoParams_GetColorResolution(¶ms))!= TRUE) { return FALSE; } #ifdef CONFIG_HMDI_JZ4780_DEBUG printk("jz4780 hdmi %s %d video configured\n",__func__,__LINE_); #endif if (video_Configure(api_mBaseAddress, ¶ms, api_mDataEnablePolarity, FALSE) != TRUE) { return FALSE; } if ((api_mCurrentState < API_HPD) || (api_mCurrentState > API_EDID_READ)) { /* if EDID read do not re-read, if HPDetected, keep in same state * otherwise, set to INIT */ api_mCurrentState = API_INIT; } /* * By default no pixel repetition and color resolution is 8 */ #ifdef CONFIG_HMDI_JZ4780_DEBUG printk("jz4780 hdmi %s %d control configured\n",__func__,__LINE_); #endif if (control_Configure(api_mBaseAddress, pixelClock, 0, 8, 0, 0, 0, 0) != TRUE) { return FALSE; } /* send AVMUTE SET (optional) */ #ifdef CONFIG_HMDI_JZ4780_DEBUG printk("jz4780 hdmi %s %d phy configured\n",__func__,__LINE_); #endif #if 0 /* enable interrupts */ access_CoreWriteByte(0x0, 0x10D2); access_CoreWriteByte(0x0, 0x10D6); access_CoreWriteByte(0x0, 0x10DA); access_CoreWriteByte(0x0, 0x0180); #endif #if 0 access_CoreWriteByte(~0x4, 0x10D2); //audio packets access_CoreWriteByte(0x0, 0x0180); //intc mute #endif api_phy_enable(PHY_ENABLE_HPD); control_InterruptMute(api_mBaseAddress, 0); if (system_InterruptHandlerRegister(TX_INT, api_EventHandler, NULL) == TRUE) { printk("=====>enable TX_INT in %s:%d\n", __func__, __LINE__); //return system_InterruptEnable(TX_INT); return TRUE; } return FALSE; }