/**
* FixPsp4Ehang
*
*
* @retval VOID
*
*/
VOID
FixPsp4Ehang (
OUT VOID
)
{
UINT8 Value8;
UINT32 IoApicNumber;
AMD_CONFIG_PARAMS *StdHeader;
FCH_DATA_BLOCK *pFchPolicy;
pFchPolicy = &gFchInitInSmm.FchPolicy;
StdHeader = pFchPolicy->StdHeader;
//FCH_DEADLOOP ();
ACPIMMIO32 (FCH_AOACx94S013_CONTROL) |= FCH_AOACx94S013_CONTROL_ARBITER_DIS + FCH_AOACx94S013_CONTROL_INTERRUPT_DIS;
ACPIMMIO32 (0xFEC00000) = 0x3E;
ACPIMMIO32 (0xFEC00010) = 0xFF;
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGED, &Value8, StdHeader);
ACPIMMIO32 (0xFEC00020) = 0x17;
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGED, &Value8, StdHeader);
IoApicNumber = ACPIMMIO32 (0xFEC00020);
for (IoApicNumber = 0; IoApicNumber < 24; IoApicNumber++) {
ACPIMMIO32 (0xFEC00000) = 0x10 + (IoApicNumber << 1);
ACPIMMIO32 (0xFEC00010) = BIT16;
}
}
/**< cimFchStall - Reserved */
VOID
CimFchStall (
IN UINT32 uSec,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 timerAddr;
UINT32 startTime;
UINT32 elapsedTime;
LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
if ( timerAddr == 0 ) {
uSec = uSec / 2;
while ( uSec != 0 ) {
LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader);
uSec--;
}
} else {
LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
for ( ;; ) {
LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
if ( elapsedTime < startTime ) {
elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
} else {
elapsedTime = elapsedTime - startTime;
}
if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
break;
}
}
}
}
/**
* FchInitEnvIr - Config Ir controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvIr (
IN VOID *FchDataPtr
)
{
IR_CONFIG FchIrConfig;
UINT8 FchIrPinControl;
UINT8 Data;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FchIrConfig = LocalCfgPtr->Ir.IrConfig;
FchIrPinControl = LocalCfgPtr->Ir.IrPinControl;
//
//IR init Logical device 0x05
//
if (FchIrConfig != IrDisable) {
EnterEcConfig (StdHeader);
RwEc8 (0x07, 0x00, 0x05, StdHeader); ///Select logical device 05, IR controller
RwEc8 (0x60, 0x00, 0x05, StdHeader); ///Set Base Address to 550h
RwEc8 (0x61, 0x00, 0x50, StdHeader);
RwEc8 (0x70, 0xF0, 0x05, StdHeader); ///Set IRQ to 05h
RwEc8 (0x30, 0x00, 0x01, StdHeader); ///Enable logical device 5, IR controller
Data = 0xAB;
LibAmdIoWrite (AccessWidth8, 0x550, &Data, StdHeader);
LibAmdIoRead (AccessWidth8, 0x551, &Data, StdHeader);
Data = (UINT8) (FchIrPinControl & 0xFC); ///Take out enable bits
Data |= FchIrPinControl & FchIrConfig & 0x03; ///Put back enable bits
LibAmdIoWrite (AccessWidth8, 0x551, &Data, StdHeader);
ExitEcConfig (StdHeader);
Data = 0xA0; /// EC APIC index
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, StdHeader);
Data = 0x05; /// IRQ5
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, StdHeader);
} else {
EnterEcConfig (StdHeader);
RwEc8 (0x07, 0x00, 0x05, StdHeader); ///Select logical device 05, IR controller
RwEc8 (0x30, 0x00, 0x00, StdHeader); ///Disable logical device 5, IR controller
Data = 0xAB;
LibAmdIoWrite (AccessWidth8, 0x550, &Data, StdHeader);
LibAmdIoRead (AccessWidth8, 0x551, &Data, StdHeader);
Data = ((UINT8) FchIrPinControl) & 0xFC; //Clear Enable bits
LibAmdIoWrite (AccessWidth8, 0x551, &Data, StdHeader);
ExitEcConfig (StdHeader);
}
}
/**
* Clear EnableCf8ExtCfg on all socket
*
* Clear F3x8C bit 14 EnableCf8ExtCfg
*
* @param[in] StdHeader Config handle for library and services
*
*
*/
VOID
DisableCf8ExtCfg (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
PCI_ADDR PciAddress;
UINT32 Socket;
UINT32 Module;
UINT32 PciData;
UINT32 LegacyPciAccess;
ASSERT (IsBsp (StdHeader, &AgesaStatus));
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CFG_HIGH_REG;
LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
// read from PCI register
LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
LibAmdIoRead (AccessWidth32, IOCFC, &PciData, StdHeader);
// Disable Cf8ExtCfg
PciData &= 0xFFFFBFFF;
// write to PCI register
LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
LibAmdIoWrite (AccessWidth32, IOCFC, &PciData, StdHeader);
}
}
}
}
/**
* sataSetIrqIntResource - Config SATA IRQ/INT# resource
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] StdHeader
*
*/
VOID
SataSetIrqIntResource (
IN VOID *FchDataPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 ValueByte;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
//
// IRQ14/IRQ15 come from IDE or SATA
//
ValueByte = 0x08;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &ValueByte, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader);
ValueByte = ValueByte & 0x0F;
if (LocalCfgPtr->Sata.SataClass == SataLegacyIde) {
ValueByte = ValueByte | 0x50;
} else {
if (LocalCfgPtr->Sata.SataIdeMode == 1) {
//
// Both IDE & SATA set to Native mode
//
ValueByte = ValueByte | 0xF0;
}
}
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader);
}
/*++
Routine Description:
Arguments:
DispatchHandle - The handle of this callback, obtained when registering
DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
Returns:
None.
--*/
EFI_STATUS
EFIAPI
AmdSmiS3SleepEntryCallback (
IN EFI_HANDLE DispatchHandle,
IN FCH_SMM_SX_REGISTER_CONTEXT *DispatchContext
)
{
UINT8 Index;
UINT8 *pData;
FCH_DATA_BLOCK *pFchPolicy;
pFchPolicy = &gFchInitInSmm.FchPolicy;
// Save entire FCH PCI IRQ routing space (C00/C01)
pData = mFchPciIrqRoutingTable;
Index = 0xFF;
do {
Index++;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Index, NULL);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, pData++, NULL);
} while (Index != 0xFF);
//Put Usb3 to S0 power rail
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEE, AccessWidth8, ~(BIT0 + BIT1), (BIT1 + BIT0));
BackUpCG2 ();
FixPsp4Ehang ();
return EFI_SUCCESS;
}
/**
* FchSataDriveDetectionFpga
*
* @param[in] LocalCfgPtr
* @param[in] Bar5
*
*/
VOID
FchSataDriveDetectionFpga (
IN FCH_DATA_BLOCK *LocalCfgPtr,
IN UINT32 *Bar5
)
{
UINT32 SataBarFpgaInfo;
UINT8 PortNum;
UINT8 SataFpaPortType;
UINT16 IoBase;
UINT32 SataFpgaLoopVarWord;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = LocalCfgPtr->StdHeader;
TRACE ((DMSG_FCH_TRACE, "FCH - Entering sata drive detection procedure\n\n"));
TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X \n", *pBar5));
for ( PortNum = 0; PortNum < 4; PortNum++ ) {
ReadMem (*Bar5 + FCH_SATA_BAR5_REG128 + PortNum * 0x80, AccWidthUint32, &SataBarFpgaInfo);
if ( ( SataBarFpgaInfo & 0x0F ) == 0x03 ) {
if ( PortNum & BIT0 ) {
//this port belongs to secondary channel
ReadPci (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG18), AccWidthUint16, &IoBase);
} else {
//this port belongs to primary channel
ReadPci (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG10), AccWidthUint16, &IoBase);
}
//if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
IoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (PortNum & BIT0) << 7)) & 0x80 )) );
}
if ( PortNum & BIT1 ) {
//this port is slave
SataFpaPortType = 0xB0;
} else {
//this port is master
SataFpaPortType = 0xA0;
}
IoBase &= 0xFFF8;
LibAmdIoWrite (AccessWidth8, IoBase + 6, &SataFpaPortType, StdHeader);
//Wait in loop for 30s for the drive to become ready
for ( SataFpgaLoopVarWord = 0; SataFpgaLoopVarWord < 300000; SataFpgaLoopVarWord++ ) {
LibAmdIoRead (AccessWidth8, IoBase + 7, &SataFpaPortType, StdHeader);
if ( (SataFpaPortType & 0x88) == 0 ) {
break;
}
FchStall (100, StdHeader);
}
}
}
}
VOID
GnbLibIoRead (
IN UINT16 Address,
IN ACCESS_WIDTH Width,
OUT VOID *Value,
IN VOID *StdHeader
)
{
LibAmdIoRead (Width, Address, Value, StdHeader);
}
/**
* ReadEc8 - Read EC register data
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Read Data Buffer
* @param[in] StdHeader
*
*/
VOID
ReadEc8 (
IN UINT8 Address,
IN UINT8 *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 EcIndexPortDword;
ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
EcIndexPortDword &= ~(BIT0);
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &Address, StdHeader);
LibAmdIoRead (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
}
/**
* Read PCI config space
*
*
* @param[in] AccessWidth Access width
* @param[in] PciAddress Pci address
* @param[in] Value Pointer to data
* @param[in] StdHeader Standard configuration header
*
*/
VOID
LibAmdPciRead (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR PciAddress,
OUT VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Address32;
Address32 = BIT31 + (UINT32) ((PciAddress.Address.Bus << 16) + \
(PciAddress.Address.Device << 11) + \
(PciAddress.Address.Function << 8) + \
(PciAddress.Address.Register & 0xFF));
LibAmdIoWrite (AccessWidth32, CFG_ADDR_PORT, &Address32, StdHeader);
LibAmdIoRead (AccessWidth, CFG_DATA_PORT, Value, StdHeader);
}
EFI_STATUS
EFIAPI
AmdSmiAcpiOffCallback (
IN EFI_HANDLE DispatchHandle,
IN FCH_SMM_SW_REGISTER_CONTEXT *DispatchContext
)
{
UINT16 AcpiPmbase;
UINT32 ddValue;
GetFchAcpiPmBase (&AcpiPmbase, NULL);
// Turn off SCI
LibAmdIoRead (AccessWidth32, AcpiPmbase + R_FCH_ACPI_PM_CONTROL, &ddValue, NULL);
ddValue &= ~BIT0;
LibAmdIoWrite (AccessWidth32, AcpiPmbase + R_FCH_ACPI_PM_CONTROL, &ddValue, NULL);
return EFI_SUCCESS;
}
/*********************************************************************************
* Name: FchSataOnRecovery
*
* Description
*
*
* Input
* FchPrivate : FCH PEI private data structure
* SataBar0 : BAR0 register value of Sata controller
* SataBar5 : BAR5 register value of Sata controller
*
* Output
*
*
*********************************************************************************/
EFI_STATUS
FchSataOnRecovery (
IN FCH_PEI_PRIVATE FchPrivate,
IN UINT32 SataBar0,
IN UINT32 SataBar5
)
{
UINT8 ValueByte;
AMD_CONFIG_PARAMS StdHeader;
StdHeader = FchPrivate.StdHdr;
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, 0xff, BIT0, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG44), AccessWidth8, 0xff, BIT0, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG44 + 2), AccessWidth8, 0, 0x20, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, 0xff, BIT4, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, 0xff, BIT7, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG4C + 3), AccessWidth8, 0x07, 0xF8, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG4C), AccessWidth32, (UINT32) (~ (0xF8 << 26)), (UINT32) (0xF8 << 26), &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018F40, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_DID, &StdHeader);
ValueByte = 0x08;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &ValueByte, &StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, &StdHeader);
//
// SATA PHY Programming Sequence
//
FchRecoveryProgramSataPhy (&StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG10), AccessWidth32, BIT0, SataBar0, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG14), AccessWidth32, BIT0, SataBar0 + 0x100, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG18), AccessWidth32, BIT0, SataBar0 + 0x200, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG1C), AccessWidth32, BIT0, SataBar0 + 0x300, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG20), AccessWidth32, BIT0, SataBar0 + 0x400, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG24), AccessWidth32, 0xff, SataBar5, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth8, 0, BIT0 + BIT1, &StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, ~BIT0, 0, &StdHeader);
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
AmdSmiAcpiOnCallback (
IN EFI_HANDLE DispatchHandle,
IN FCH_SMM_SW_REGISTER_CONTEXT *DispatchContext
)
{
FCH_DATA_BLOCK *pFchPolicy;
UINT16 AcpiPmbase;
UINT8 dbIndex;
UINT8 dbIrq;
UINT32 ddValue;
//EFI_DEADLOOP ();
// WriteIO16 (0x80, 0xAACC);
GetFchAcpiPmBase (&AcpiPmbase, NULL);
pFchPolicy = &gFchInitInSmm.FchPolicy;
FchSmmAcpiOn (pFchPolicy);
// Disable all GPE events and clear all GPE status
ddValue = 0;
LibAmdIoWrite (AccessWidth32, AcpiPmbase + R_FCH_ACPI_EVENT_ENABLE, &ddValue, NULL);
LibAmdIoWrite (AccessWidth32, AcpiPmbase + R_FCH_ACPI_EVENT_STATUS, &ddValue, NULL);
// Set ACPI IRQ to IRQ9 for non-APIC OSes
dbIndex = 0x10; // PIC - SCI
dbIrq = 9;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &dbIndex, NULL);
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &dbIrq, NULL);
dbIndex |= BIT7; // IOAPIC - SCI
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &dbIndex, NULL);
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &dbIrq, NULL);
// Finally enable SCI
LibAmdIoRead (AccessWidth32, AcpiPmbase + R_FCH_ACPI_PM_CONTROL, &ddValue, NULL);
ddValue |= BIT0;
LibAmdIoWrite (AccessWidth32, AcpiPmbase + R_FCH_ACPI_PM_CONTROL, &ddValue, NULL);
return EFI_SUCCESS;
}
/**
* Prepare an FCH AB link entry on a family 15h Carrizo core.
*
* @param[in] CurrentEntry Current entry to process
*
* @return Pointer to next table entry
*/
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessFchAbEntry (
IN CS_RESTORATION_ENTRY_HEADER *CurrentEntry
)
{
UINT32 RegisterIndex;
UINT64 MmioAddr;
CS_FCH_AB *FchAbEntry;
FchAbEntry = (CS_FCH_AB *) CurrentEntry;
if (FchAbEntry->Header.SaveReadValue) {
if (AbIoAddress == 0xFFFF) {
MmioAddr = 0xFED803E0;
LibAmdMemRead (AccessWidth16, MmioAddr, &AbIoAddress, NULL);
}
RegisterIndex = FchAbEntry->Address + 0xC0000000;
LibAmdIoWrite (AccessWidth32, AbIoAddress, &RegisterIndex, NULL);
LibAmdIoRead (AccessWidth32, AbIoAddress + 4, &FchAbEntry->Value, NULL);
}
FchAbEntry++;
return &FchAbEntry->Header;
}
VOID
ReadECmsg (
IN UINT8 Address,
IN UINT8 OpFlag,
OUT VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Index;
OpFlag = OpFlag & 0x7f;
if (OpFlag == 0x02) {
OpFlag = 0x03;
}
for (Index = 0; Index <= OpFlag; Index++) {
/// EC_LDN9_MAILBOX_BASE_ADDRESS
LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader);
Address++;
/// EC_LDN9_MAILBOX_BASE_ADDRESS
LibAmdIoRead (AccessWidth8, 0x3F, (UINT8 *)Value + Index, StdHeader);
}
}
/**
* Send byte to Serial Port
*
* Before use this routine, please make sure Serial Communications Chip have been initialed
*
* @param[in] ByteSended Byte to be sended
*
* @retval TRUE Byte sended successfully
* @retval FALSE Byte sended failed
*
**/
BOOLEAN
AmdIdsSerialSendByte (
IN CHAR8 ByteSended
)
{
UINT32 RetryCount;
UINT8 Value;
//Wait until LSR.Bit5 (Transmitter holding register Empty)
RetryCount = 200;
do {
LibAmdIoRead (AccessWidth8, IDS_SERIAL_PORT_LSR, &Value, NULL);
RetryCount--;
} while (((Value & IDS_LSR_TRANSMIT_HOLDING_REGISTER_EMPTY_MASK) == 0) &&
(RetryCount > 0));
if (RetryCount == 0) {
//Time expired
return FALSE;
} else {
LibAmdIoWrite (AccessWidth8, IDS_SERIAL_PORT, &ByteSended, NULL);
return TRUE;
}
}
/**
* FchInitResetHwAcpi - Config HwAcpi controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetHwAcpi (
IN VOID *FchDataPtr
)
{
UINT16 SmbusBase;
UINT8 Value;
UINT16 AsfPort;
UINT32 GeventEnableBits;
UINT32 GeventValue;
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Set Build option into SB
//
WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.FchBldCfg->CfgSioPmeBaseAddress), StdHeader);
//
// Enabled SMBUS0/SMBUS1 (ASF) Base Address
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1]
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus1BaseAddress) + BIT0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgCpuControlBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr) + 8);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.FchBldCfg->CfgWatchDogTimerBase));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, (UINT32)~(BIT1 + BIT2), 0); ///clear BIT[2:1]
SmbusBase = (UINT16) (UserOptions.FchBldCfg->CfgSmbus0BaseAddress);
Value = 0x00;
LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader);
ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader);
if (UserOptions.FchBldCfg->CfgFchGpioControl != NULL) {
ProgramFchGpioTbl ((UserOptions.FchBldCfg->CfgFchGpioControl), LocalCfgPtr);
}
if (UserOptions.FchBldCfg->CfgFchSataPhyControl != NULL) {
ProgramFchSataPhyTbl ((UserOptions.FchBldCfg->CfgFchSataPhyControl), LocalCfgPtr);
}
//
// RTC Workaround for Daylight saving time enable bit
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, BIT0 ); // Enable DltSavEnable
Value = 0x0B;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= 0xFE;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, 0 ); // Disable DltSavEnable
//
// Prevent RTC error
//
Value = 0x0A;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= 0xEF;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value = 0x08;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
//
Value = Value | 0x0A;
}
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( UserOptions.FchBldCfg->CfgFchRtcWorkAround ) {
Value = RTC_WORKAROUND_SECOND;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
if ( Value > RTC_VALID_SECOND_VALUE ) {
Value = RTC_SECOND_RESET_VALUE;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
}
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= RTC_SECOND_LOWER_NIBBLE;
if ( Value > RTC_VALID_SECOND_VALUE_LN ) {
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value = RTC_SECOND_RESET_VALUE;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
}
}
Value = 0x09;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
//
Value = Value & 0xF9;
}
if ( LocalCfgPtr->LegacyFree ) {
//
// Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
//
Value = Value & 0x9F;
}
//
// Enabled IRQ input
//
Value = Value | BIT4;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
AsfPort = ((UINT16) UserOptions.FchBldCfg->CfgSmbus1BaseAddress & 0xFFF0);
if ( AsfPort != 0 ) {
UINT8 dbValue;
dbValue = 0x70;
LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader);
dbValue = 0x2F;
LibAmdIoWrite (AccessWidth8, AsfPort + 0x0A, &dbValue, StdHeader);
}
//
// PciExpWakeStatus workaround
//
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort);
AsfPort++;
ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG04, AccessWidth32, &GeventEnableBits);
ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG00, AccessWidth32, &GeventValue);
if ( (GeventValue & GeventEnableBits) != 0 ) {
Value = 0x40;
LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader);
}
LibAmdIoRead (AccessWidth8, AsfPort, &Value, StdHeader);
if ((Value & (BIT2 + BIT0)) != 0) {
Value = 0x40;
LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader);
}
//
// Set ACPIMMIO by OEM Input table
//
if ( LocalCfgPtr->OemResetProgrammingTablePtr != NULL ) {
ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->OemResetProgrammingTablePtr), StdHeader);
}
}
/**
* FchInitResetHwAcpi - Config HwAcpi controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetHwAcpi (
IN VOID *FchDataPtr
)
{
UINT16 SmbusBase;
UINT8 Value;
UINT16 AsfPort;
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Set Build option into SB
//
WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.CfgSioPmeBaseAddress), StdHeader);
//
// Enabled SMBUS0/SMBUS1 (ASF) Base Address
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1]
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, 06, (UserOptions.CfgSmbus1BaseAddress) + BIT0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.CfgAcpiPm1EvtBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.CfgAcpiPm1CntBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.CfgAcpiPmTmrBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.CfgCpuControlBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.CfgAcpiGpe0BlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, 00, (UserOptions.CfgAcpiPmaCntBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr) + 8);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.CfgWatchDogTimerBase));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, ~(BIT1 + BIT2), 0); ///clear BIT[2:1]
SmbusBase = (UINT16) (UserOptions.CfgSmbus0BaseAddress);
Value = 0x00;
LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader);
ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader);
//
// Prevent RTC error
//
Value = 0x0A;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= 0xEF;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value = 0x08;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
//
Value = Value | 0x0A;
}
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
Value = 0x09;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
//
Value = Value & 0xF9;
}
if ( LocalCfgPtr->LegacyFree ) {
//
// Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
//
Value = Value & 0x9F;
}
//
// Enabled IRQ input
//
Value = Value | BIT4;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
AsfPort = ((UINT16) UserOptions.CfgSmbus1BaseAddress & 0xFFF0);
if ( AsfPort != 0 ) {
UINT8 dbValue;
dbValue = 0x70;
LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader);
}
}
