static void wait_for_completion(unsigned long base)
{
#ifdef CONFIG_TI_I2C_WAIT_FOR_BUSY_WAR
/* XXX: Ugly workaround:
* Busy flag takes a while to be asserted, so we wait for it.
* Assumption is that the operation is long enough so we won't
* miss it
*/
while (!MAP_I2CMasterBusy(base));
#endif
while (MAP_I2CMasterBusy(base));
}
uint8_t TwoWire::I2CTransact(unsigned long ulCmd)
{
MAP_I2CMasterIntClearEx(I2C_BASE, MAP_I2CMasterIntStatusEx(I2C_BASE, false));
MAP_I2CMasterTimeoutSet(I2C_BASE, I2C_TIMEOUT_VAL);
MAP_I2CMasterControl(I2C_BASE, ulCmd);
while((MAP_I2CMasterIntStatusEx(I2C_BASE, false)
& (I2C_INT_MASTER | I2C_MRIS_CLKTOUT)) == 0) {
if(!MAP_I2CMasterBusy(I2C_BASE)) return -1;
}
/* Check for any errors in transfer */
if(MAP_I2CMasterErr(I2C_BASE) != I2C_MASTER_ERR_NONE) {
switch(ulCmd) {
case I2C_MASTER_CMD_BURST_SEND_START:
case I2C_MASTER_CMD_BURST_SEND_CONT:
case I2C_MASTER_CMD_BURST_SEND_STOP:
MAP_I2CMasterControl(I2C_BASE,
I2C_MASTER_CMD_BURST_SEND_ERROR_STOP);
break;
case I2C_MASTER_CMD_BURST_RECEIVE_START:
case I2C_MASTER_CMD_BURST_RECEIVE_CONT:
case I2C_MASTER_CMD_BURST_RECEIVE_FINISH:
MAP_I2CMasterControl(I2C_BASE,
I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP);
break;
default:
break;
}
return 0;
}
return -1;
}
static inline int I2C_WaitForBus(unsigned long errorCmd)
{
while (MAP_I2CMasterBusy(I2CBase));
if (MAP_I2CMasterErr(I2CBase))
{
MAP_I2CMasterControl(I2CBase, errorCmd);
I2C_Error(__FILE__, __LINE__);
return 1;
}
return 0;
}
