STATIC void pyb_sleep_flash_powerdown (void) { uint32_t status; // Enable clock for SSPI module MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); // Reset SSPI at PRCM level and wait for reset to complete MAP_PRCMPeripheralReset(PRCM_SSPI); while(!MAP_PRCMPeripheralStatusGet(PRCM_SSPI)); // Reset SSPI at module level MAP_SPIReset(SSPI_BASE); // Configure SSPI module MAP_SPIConfigSetExpClk (SSPI_BASE, PRCMPeripheralClockGet(PRCM_SSPI), 20000000, SPI_MODE_MASTER,SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | SPI_CS_ACTIVELOW | SPI_WL_8)); // Enable SSPI module MAP_SPIEnable(SSPI_BASE); // Enable chip select for the spi flash. MAP_SPICSEnable(SSPI_BASE); // Wait for the spi flash do { // Send the status register read instruction and read back a dummy byte. MAP_SPIDataPut(SSPI_BASE, SPIFLASH_INSTR_READ_STATUS); MAP_SPIDataGet(SSPI_BASE, &status); // Write a dummy byte then read back the actual status. MAP_SPIDataPut(SSPI_BASE, 0xFF); MAP_SPIDataGet(SSPI_BASE, &status); } while ((status & 0xFF) == SPIFLASH_STATUS_BUSY); // Disable chip select for the spi flash. MAP_SPICSDisable(SSPI_BASE); // Start another CS enable sequence for Power down command. MAP_SPICSEnable(SSPI_BASE); // Send Deep Power Down command to spi flash MAP_SPIDataPut(SSPI_BASE, SPIFLASH_INSTR_DEEP_POWER_DOWN); // Disable chip select for the spi flash. MAP_SPICSDisable(SSPI_BASE); }
Fd_t spi_Open(char *ifName, unsigned long flags) { unsigned long ulBase; unsigned long ulSpiBitRate; tROMVersion* pRomVersion = (tROMVersion *)(ROM_VERSION_ADDR); //NWP master interface ulBase = LSPI_BASE; //Enable MCSPIA2 MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK); //Disable Chip Select MAP_SPICSDisable(ulBase); //Disable SPI Channel MAP_SPIDisable(ulBase); // Reset SPI MAP_SPIReset(ulBase); // // Configure SPI interface // if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_21 ) { ulSpiBitRate = SPI_RATE_13M; } else if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_32) { ulSpiBitRate = SPI_RATE_13M; } else if(pRomVersion->ucMinorVerNum >= ROM_VER_PG1_33) { ulSpiBitRate = SPI_RATE_20M; } MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI), ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | SPI_CS_ACTIVEHIGH | SPI_WL_32)); if(MAP_PRCMPeripheralStatusGet(PRCM_UDMA)) { g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0; } else { g_ucDMAEnabled = 0; } #ifdef SL_CPU_MODE g_ucDMAEnabled = 0; #endif if(g_ucDMAEnabled) { memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout)); // Set DMA channel cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX); cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX); MAP_SPIFIFOEnable(ulBase,SPI_RX_FIFO); MAP_SPIFIFOEnable(ulBase,SPI_TX_FIFO); MAP_SPIDmaEnable(ulBase,SPI_RX_DMA); MAP_SPIDmaEnable(ulBase,SPI_TX_DMA); MAP_SPIFIFOLevelSet(ulBase,1,1); #if defined(SL_PLATFORM_MULTI_THREADED) osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1); MAP_SPIIntEnable(ulBase,SPI_INT_EOW); osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1); #else MAP_IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler); MAP_IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1); MAP_IntEnable(INT_LSPI); MAP_SPIIntEnable(ulBase,SPI_INT_EOW); g_cDummy = 0x0; #endif } MAP_SPIEnable(ulBase); g_SpiFd = 1; return g_SpiFd; }