int main() {
MAP_IntVTableBaseSet((unsigned long) &g_pfnVectors[0]);
MAP_IntEnable(FAULT_SYSTICK);
MAP_IntMasterEnable();
PRCMCC3200MCUInit();
cc3200_leds_init();
/* Console UART init. */
MAP_PRCMPeripheralClkEnable(CONSOLE_UART_PERIPH, PRCM_RUN_MODE_CLK);
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* PIN_55 -> UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* PIN_57 -> UART0_RX */
MAP_UARTConfigSetExpClk(
CONSOLE_UART, MAP_PRCMPeripheralClockGet(CONSOLE_UART_PERIPH),
CONSOLE_BAUD_RATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
MAP_UARTFIFODisable(CONSOLE_UART);
setvbuf(stdout, NULL, _IONBF, 0);
setvbuf(stderr, NULL, _IONBF, 0);
VStartSimpleLinkSpawnTask(8);
osi_TaskCreate(v7_task, (const signed char *) "v7", V7_STACK_SIZE + 256, NULL,
3, NULL);
osi_TaskCreate(blinkenlights_task, (const signed char *) "blink", 256, NULL,
9, NULL);
osi_start();
return 0;
}
void GPS_init()
{
dbg_printf("Initializing GPS module...");
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART);
MAP_GPIOPinConfigure(GPIO_PA0_U0RX);
MAP_GPIOPinConfigure(GPIO_PA1_U0TX);
MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
MAP_UARTConfigSetExpClk(UART_BASE, MAP_SysCtlClockGet(), UART_SPEED, UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE);
MAP_UARTDisable(UART_BASE);
MAP_UARTTxIntModeSet(UART_BASE, UART_TXINT_MODE_EOT);
MAP_UARTIntEnable(UART_BASE, UART_INT_RX | UART_INT_TX);
MAP_IntEnable(INT_UART);
MAP_UARTEnable(UART_BASE);
MAP_UARTFIFODisable(UART_BASE);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
//
MAP_IntEnable(INT_GPIOG);
// Настроить прерывания на PPS
MAP_GPIOIntTypeSet(GPIO_PORTG_BASE, GPIO_PIN_7, GPIO_FALLING_EDGE);
MAP_GPIOPinIntEnable(GPIO_PORTG_BASE, GPIO_PIN_7);
//
if (tn_task_create(&task_GPS_tcb, &task_GPS_func, TASK_GPS_PRI,
&task_GPS_stk[TASK_GPS_STK_SZ - 1], TASK_GPS_STK_SZ, 0,
TN_TASK_START_ON_CREATION) != TERR_NO_ERR)
{
dbg_puts("tn_task_create(&task_GPS_tcb) error");
goto err;
}
// Настроить прерывания на PPS
//MAP_IntEnable(INT_GPIOG);
//MAP_GPIOIntTypeSet(GPIO_PORTG_BASE, GPIO_PIN_7, GPIO_FALLING_EDGE);
//MAP_GPIOPinIntEnable(GPIO_PORTG_BASE, GPIO_PIN_7);
dbg_puts("[done]");
return;
err:
dbg_trace();
tn_halt();
}
void UART1IntInit(){
//configure Uart
MAP_UARTConfigSetExpClk(UARTA1_BASE, MAP_PRCMPeripheralClockGet(PRCM_UARTA1),
UART_BAUD_RATE, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));
UARTEnable(UARTA1_BASE);
// Disable FIFO so RX interrupt triggers on any character
MAP_UARTFIFODisable(UARTA1_BASE);
// Set interrupt handlers
MAP_UARTIntRegister(UARTA1_BASE,receiveMessage);
// Clear any interrupts that may have been present
MAP_UARTIntClear(UARTA1_BASE, UART_INT_RX);
// Enable interrupt
MAP_UARTIntEnable(UARTA1_BASE, UART_INT_RX|UART_INT_RT);
UARTFIFOEnable(UARTA1_BASE);
}
void cc32xx_uart_early_init(int uart_no, int baud_rate) {
if (uart_no < 0) return;
uint32_t base = cc32xx_uart_get_base(uart_no);
uint32_t periph;
if (uart_no == 0) {
periph = PRCM_UARTA0;
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* UART0_RX */
} else if (uart_no == 1) {
periph = PRCM_UARTA1;
MAP_PinTypeUART(PIN_07, PIN_MODE_5); /* UART1_TX */
MAP_PinTypeUART(PIN_08, PIN_MODE_5); /* UART1_RX */
} else {
return;
}
MAP_PRCMPeripheralClkEnable(periph, PRCM_RUN_MODE_CLK);
MAP_UARTConfigSetExpClk(
base, MAP_PRCMPeripheralClockGet(periph), baud_rate,
UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE);
MAP_UARTFIFODisable(base);
MAP_UARTIntDisable(base, ~0); /* Start with ints disabled. */
}
int main(void) {
MAP_IntVTableBaseSet((unsigned long) &int_vectors[0]);
MAP_IntMasterEnable();
PRCMCC3200MCUInit();
/* Console UART init. */
#ifndef NO_DEBUG
MAP_PRCMPeripheralClkEnable(DEBUG_UART_PERIPH, PRCM_RUN_MODE_CLK);
#if MIOT_DEBUG_UART == 0
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* UART0_RX */
#else
MAP_PinTypeUART(PIN_07, PIN_MODE_5); /* UART1_TX */
MAP_PinTypeUART(PIN_08, PIN_MODE_5); /* UART1_RX */
#endif
MAP_UARTConfigSetExpClk(
DEBUG_UART_BASE, MAP_PRCMPeripheralClockGet(DEBUG_UART_PERIPH),
MIOT_DEBUG_UART_BAUD_RATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
MAP_UARTFIFOLevelSet(DEBUG_UART_BASE, UART_FIFO_TX1_8, UART_FIFO_RX4_8);
MAP_UARTFIFODisable(DEBUG_UART_BASE);
#endif
dbg_puts("\r\n\n");
if (sl_Start(NULL, NULL, NULL) < 0) abort();
dbg_putc('S');
int cidx = get_active_boot_cfg_idx();
if (cidx < 0) abort();
dbg_putc('0' + cidx);
struct boot_cfg cfg;
if (read_boot_cfg(cidx, &cfg) < 0) abort();
dbg_puts(cfg.app_image_file);
dbg_putc('@');
print_addr(cfg.app_load_addr);
/*
* Zero memory before loading.
* This should provide proper initialisation for BSS, wherever it is.
*/
uint32_t *pstart = (uint32_t *) 0x20000000;
uint32_t *pend = (&_text_start - 0x100 /* our stack */);
for (uint32_t *p = pstart; p < pend; p++) *p = 0;
if (load_image(cfg.app_image_file, (_u8 *) cfg.app_load_addr) != 0) {
abort();
}
dbg_putc('.');
sl_Stop(0);
print_addr(*(((uint32_t *) cfg.app_load_addr) + 1));
dbg_puts("\r\n\n");
MAP_IntMasterDisable();
MAP_IntVTableBaseSet(cfg.app_load_addr);
run(cfg.app_load_addr); /* Does not return. */
abort();
return 0; /* not reached */
}
static void uart_int() {
int c = UARTCharGet(CONSOLE_UART);
struct prompt_event pe = {.type = PROMPT_CHAR_EVENT, .data = (void *) c};
osi_MsgQWrite(&s_v7_q, &pe, OSI_NO_WAIT);
MAP_UARTIntClear(CONSOLE_UART, UART_INT_RX);
}
void sj_prompt_init_hal(struct v7 *v7) {
(void) v7;
}
static void v7_task(void *arg) {
struct v7 *v7 = s_v7;
printf("\n\nSmart.JS for CC3200\n");
osi_MsgQCreate(&s_v7_q, "V7", sizeof(struct prompt_event), 32 /* len */);
osi_InterruptRegister(CONSOLE_UART_INT, uart_int, INT_PRIORITY_LVL_1);
MAP_UARTIntEnable(CONSOLE_UART, UART_INT_RX);
sl_Start(NULL, NULL, NULL);
v7 = s_v7 = init_v7(&v7);
sj_init_timers(v7);
sj_init_v7_ext(v7);
init_wifi(v7);
if (init_fs(v7) != 0) {
fprintf(stderr, "FS initialization failed.\n");
}
mongoose_init();
sj_init_http(v7);
init_i2cjs(v7);
/* Common config infrastructure. Mongoose & v7 must be initialized. */
init_device(v7);
v7_val_t res;
if (v7_exec_file(v7, "sys_init.js", &res) != V7_OK) {
fprintf(stderr, "Error: ");
v7_fprint(stderr, v7, res);
}
sj_prompt_init(v7);
while (1) {
struct prompt_event pe;
mongoose_poll(MONGOOSE_POLL_LENGTH_MS);
if (osi_MsgQRead(&s_v7_q, &pe, V7_POLL_LENGTH_MS) != OSI_OK) continue;
switch (pe.type) {
case PROMPT_CHAR_EVENT: {
sj_prompt_process_char((char) ((int) pe.data));
break;
}
case V7_INVOKE_EVENT: {
struct v7_invoke_event_data *ied =
(struct v7_invoke_event_data *) pe.data;
_sj_invoke_cb(v7, ied->func, ied->this_obj, ied->args);
v7_disown(v7, &ied->args);
v7_disown(v7, &ied->this_obj);
v7_disown(v7, &ied->func);
free(ied);
break;
}
}
}
}
/* Int vector table, defined in startup_gcc.c */
extern void (*const g_pfnVectors[])(void);
void device_reboot(void) {
sj_system_restart();
}
int main() {
MAP_IntVTableBaseSet((unsigned long) &g_pfnVectors[0]);
MAP_IntEnable(FAULT_SYSTICK);
MAP_IntMasterEnable();
PRCMCC3200MCUInit();
cc3200_leds_init();
/* Console UART init. */
MAP_PRCMPeripheralClkEnable(CONSOLE_UART_PERIPH, PRCM_RUN_MODE_CLK);
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* PIN_55 -> UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* PIN_57 -> UART0_RX */
MAP_UARTConfigSetExpClk(
CONSOLE_UART, MAP_PRCMPeripheralClockGet(CONSOLE_UART_PERIPH),
CONSOLE_BAUD_RATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
MAP_UARTFIFODisable(CONSOLE_UART);
setvbuf(stdout, NULL, _IONBF, 0);
setvbuf(stderr, NULL, _IONBF, 0);
VStartSimpleLinkSpawnTask(8);
osi_TaskCreate(v7_task, (const signed char *) "v7", V7_STACK_SIZE + 256, NULL,
3, NULL);
osi_TaskCreate(blinkenlights_task, (const signed char *) "blink", 256, NULL,
9, NULL);
osi_start();
return 0;
}
Uart0::Error Uart0::config_uart() {
if (is_open())
return kPortAlreadyOpen;
uint32_t data_bits_cc3200;
switch (data_bits) {
case 5:
data_bits_cc3200 = UART_CONFIG_WLEN_5;
break;
case 6:
data_bits_cc3200 = UART_CONFIG_WLEN_6;
break;
case 7:
data_bits_cc3200 = UART_CONFIG_WLEN_7;
break;
case 8:
data_bits_cc3200 = UART_CONFIG_WLEN_8;
break;
default:
return kUnsuportedFeature;
}
uint32_t stop_bits_cc3200;
switch (stop_bits) {
case 1:
stop_bits_cc3200 = UART_CONFIG_STOP_ONE;
break;
case 2:
stop_bits_cc3200 = UART_CONFIG_STOP_TWO;
break;
default:
return kUnsuportedFeature;
}
uint32_t parity_cc3200;
switch (parity) {
case kParityEven:
parity_cc3200 = UART_CONFIG_PAR_EVEN;
break;
case kParityMark:
parity_cc3200 = UART_CONFIG_PAR_ONE;
break;
case kParityNone:
parity_cc3200 = UART_CONFIG_PAR_NONE;
break;
case kParityOdd:
parity_cc3200 = UART_CONFIG_PAR_ODD;
break;
case kParitySpace:
parity_cc3200 = UART_CONFIG_PAR_ZERO;
break;
default:
return kUnsuportedFeature;
}
MAP_UARTConfigSetExpClk(UARTA0_BASE, 80000000, baud,
(data_bits_cc3200 | stop_bits_cc3200 | parity_cc3200));
/*
* Disable UART to modify the configuration.
* This is needed because the SetExpClk function enables the UART
*/
MAP_UARTDisable(UARTA0_BASE);
switch (flow_control) {
case kFlowControlNone:
MAP_UARTFlowControlSet(UARTA0_BASE, UART_FLOWCONTROL_NONE);
break;
case kFlowControlHardware:
/* Enable RTS/CTS Flow Control */
if (mode == kModeDuplex)
MAP_UARTFlowControlSet(UARTA0_BASE,
UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX);
if (mode == kModeRxOnly)
MAP_UARTFlowControlSet(UARTA0_BASE,
UART_FLOWCONTROL_RX);
if (mode == kModeTxOnly)
MAP_UARTFlowControlSet(UARTA0_BASE,
UART_FLOWCONTROL_TX);
break;
default:
return kUnsuportedFeature;
break;
}
/* Register Interrupt */
MAP_UARTIntRegister(UARTA0_BASE, isr);
/* Enable Interrupt */
MAP_UARTTxIntModeSet(UARTA0_BASE, UART_TXINT_MODE_EOT);
MAP_UARTIntClear(UARTA0_BASE, UART_INT_TX | UART_INT_RX);
uint32_t interrupts = 0;
if ((mode == kModeDuplex) || (mode == kModeTxOnly))
interrupts |= UART_INT_TX;
if ((mode == kModeDuplex) || (mode == kModeRxOnly))
interrupts |= UART_INT_RX;
MAP_UARTIntEnable(UARTA0_BASE, interrupts);
/* Enable UART */
MAP_UARTEnable(UARTA0_BASE);
/* Disable Fifo */
MAP_UARTFIFODisable(UARTA0_BASE);
return kOK;
}
