bool mgos_uart_hal_init(struct mgos_uart_state *us) {
uint32_t base = cc32xx_uart_get_base(us->uart_no);
uint32_t periph, int_no;
void (*int_handler)();
/* TODO(rojer): Configurable pin mappings? */
if (us->uart_no == 0) {
periph = PRCM_UARTA0;
int_no = INT_UARTA0;
int_handler = u0_int;
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* UART0_RX */
} else if (us->uart_no == 1) {
periph = PRCM_UARTA1;
int_no = INT_UARTA1;
int_handler = u1_int;
MAP_PinTypeUART(PIN_07, PIN_MODE_5); /* UART1_TX */
MAP_PinTypeUART(PIN_08, PIN_MODE_5); /* UART1_RX */
} else {
return false;
}
struct cc32xx_uart_state *ds =
(struct cc32xx_uart_state *) calloc(1, sizeof(*ds));
ds->base = base;
cs_rbuf_init(&ds->isr_rx_buf, CC32xx_UART_ISR_RX_BUF_SIZE);
us->dev_data = ds;
MAP_PRCMPeripheralClkEnable(periph, PRCM_RUN_MODE_CLK);
MAP_UARTIntDisable(base, ~0); /* Start with ints disabled. */
MAP_IntRegister(int_no, int_handler);
MAP_IntPrioritySet(int_no, INT_PRIORITY_LVL_1);
MAP_IntEnable(int_no);
return true;
}
static void cc32xx_int_handler(struct mgos_uart_state *us) {
if (us == NULL) return;
struct cc32xx_uart_state *ds = (struct cc32xx_uart_state *) us->dev_data;
uint32_t int_st = MAP_UARTIntStatus(ds->base, true /* masked */);
us->stats.ints++;
uint32_t int_dis = UART_TX_INTS;
if (int_st & UART_INT_OE) {
us->stats.rx_overflows++;
HWREG(ds->base + UART_O_ECR) = 0xff;
}
if (int_st & (UART_RX_INTS | UART_TX_INTS)) {
if (int_st & UART_RX_INTS) {
us->stats.rx_ints++;
struct cs_rbuf *irxb = &ds->isr_rx_buf;
cc32xx_uart_rx_bytes(ds->base, irxb);
if (us->cfg.rx_fc_type == MGOS_UART_FC_SW &&
irxb->used >= CC32xx_UART_ISR_RX_BUF_FC_THRESH && !us->xoff_sent) {
MAP_UARTCharPut(ds->base, MGOS_UART_XOFF_CHAR);
us->xoff_sent = true;
}
/* Do not disable RX ints if we have space in the ISR buffer. */
if (irxb->avail == 0) int_dis |= UART_RX_INTS;
}
if (int_st & UART_TX_INTS) us->stats.tx_ints++;
mgos_uart_schedule_dispatcher(us->uart_no, true /* from_isr */);
}
MAP_UARTIntDisable(ds->base, int_dis);
MAP_UARTIntClear(ds->base, int_st);
}
void HardwareSerial::setModule(unsigned long module)
{
MAP_UARTIntDisable(UART_BASE, UART_INT_RT | UART_INT_TX);
MAP_UARTIntUnregister(UART_BASE);
uartModule = module;
begin(baudRate);
}
/// \method deinit()
/// Turn off the UART bus.
STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in) {
pyb_uart_obj_t *self = self_in;
uint uartPerh;
switch (self->uart_id) {
case PYB_UART_0:
uartPerh = PRCM_UARTA0;
break;
case PYB_UART_1:
uartPerh = PRCM_UARTA1;
break;
default:
return mp_const_none;
}
self->enabled = false;
MAP_UARTIntDisable(self->reg, UART_INT_RX | UART_INT_RT);
MAP_UARTIntClear(self->reg, UART_INT_RX | UART_INT_RT);
MAP_UARTIntUnregister(self->reg);
MAP_UARTDisable(self->reg);
MAP_PRCMPeripheralClkDisable(uartPerh, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
return mp_const_none;
}
void Get_gps_info(GPS_INFO *gps)
{
MAP_UARTIntDisable(UART_BASE, UART_INT_RX);
memcpy(gps, &gps_info, sizeof(gps_info));
MAP_UARTIntEnable(UART_BASE, UART_INT_RX);
}
static int int_uart_rx_set_status( elua_int_resnum resnum, int status )
{
int prev = int_uart_rx_get_status( resnum );
if( status == PLATFORM_CPU_ENABLE )
MAP_UARTIntEnable( uart_base[ resnum ], uart_int_mask );
else
MAP_UARTIntDisable( uart_base[ resnum ], uart_int_mask );
return prev;
}
//------------------------------------------------------------------------------
void GPS_PPS_int_handler(void)
{
MAP_UARTIntDisable(UART_BASE, UART_INT_RX);
memcpy(&gps_info.time_now, &gps_info.time_pack, sizeof(gps_info.time_pack));
gps_pps_counter++;
MAP_UARTIntEnable(UART_BASE, UART_INT_RX);
}
void sendMessage(char str[8], int retval){
char str2[100];
int i;
for(i = 0; i < 8; i++){
str2[i] = str[i];
}
//Disables UART interrupt while sending characters
MAP_UARTIntDisable(UARTA1_BASE, UART_INT_RX | UART_INT_RT);
str2[7] = '\0';
http_post(retval, str2);
//Enables UART interrupts
MAP_UARTIntEnable(UARTA1_BASE, UART_INT_RX | UART_INT_RT);
}
//--------------------------------
void esp8266::ConfigureUART(uint32_t nBps) {
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
GPIOPinConfigure(GPIO_PC4_U1RX);
GPIOPinConfigure(GPIO_PC5_U1TX);
GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
UARTClockSourceSet(UART_BASE, UART_CLOCK_PIOSC);
SetBitrate(nBps);
MAP_UARTFIFOLevelSet(UART_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
MAP_UARTIntDisable(UART_BASE, 0xFFFFFFFF);
MAP_UARTIntEnable(UART_BASE, UART_INT_RX | UART_INT_RT);
MAP_IntEnable(UART_INT);
MAP_UARTEnable(UART_BASE);
}
//--------------------------------
void esp8266::OnTransmit() {
if (m_nTxHead != m_nTxFill) {
MAP_IntDisable(UART_INT);
while (MAP_UARTSpaceAvail(UART_BASE) && (m_nTxHead != m_nTxFill)) {
m_nTxHead = ((m_nTxHead + 1) % OutputBufferSize);
MAP_UARTCharPutNonBlocking(UART_BASE, m_cOutput[m_nTxHead]);
}
MAP_IntEnable(UART_INT);
}
if (m_nTxHead == m_nTxFill) {
MAP_UARTIntDisable(UART_BASE, UART_INT_TX);
}
}
/* for the data length and data buffer (respectively). */
void BTPSAPI HCITR_COMClose(unsigned int HCITransportID)
{
HCITR_COMDataCallback_t COMDataCallback;
unsigned long CallbackParameter;
/* Check to make sure that the specified Transport ID is valid. */
if((HCITransportID == TRANSPORT_ID) && (HCITransportOpen))
{
/* Disable the UART Interrupts. */
MAP_UARTIntDisable(UartContext.Base, UART_INT_RX | UART_INT_RT);
MAP_IntDisable(UartContext.IntBase);
/* Place the Bluetooth Device in Reset. */
MAP_GPIOPinWrite(HCI_RESET_BASE, HCI_RESET_PIN, 0);
/* Note the Callback information. */
COMDataCallback = _COMDataCallback;
CallbackParameter = _COMCallbackParameter;
/* Flag that the HCI Transport is no longer open. */
HCITransportOpen = 0;
/* Flag that there is no callback information present. */
_COMDataCallback = NULL;
_COMCallbackParameter = 0;
/* Flag that the RxThread is deleted. */
Handle = NULL;
/* Flag that the Rx Thread should delete itself. */
RxThreadDeleted = TRUE;
BTPS_SetEvent(RxDataEvent);
/* Flag that the RxThread is deleted. */
Handle = NULL;
/* Delay while the RxThread exits. */
BTPS_Delay(5);
/* All finished, perform the callback to let the upper layer know */
/* that this module will no longer issue data callbacks and is */
/* completely cleaned up. */
if(COMDataCallback)
(*COMDataCallback)(HCITransportID, 0, NULL, CallbackParameter);
/* Close the RxData event. */
BTPS_CloseEvent(RxDataEvent);
}
}
static rt_err_t rt_serial_close(rt_device_t dev)
{
struct rt_lm3s_serial* serial;
serial = (struct rt_lm3s_serial*) dev;
RT_ASSERT(serial != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* disable UART rx interrupt */
MAP_UARTIntDisable(serial->hw_base, UART_INT_RX | UART_INT_RT);
}
return RT_EOK;
}
void HardwareSerial::end()
{
unsigned long ulInt = MAP_IntMasterDisable();
flushAll();
/* If interrupts were enabled when we turned them off,
* turn them back on again. */
if(!ulInt) {
MAP_IntMasterEnable();
}
MAP_UARTIntDisable(UART_BASE, UART_INT_RT | UART_INT_TX);
MAP_UARTIntUnregister(UART_BASE);
}
void Uart0::close() {
/* Check if port is open */
if (!is_open())
return;
/* Disable Serial Port */
MAP_UARTDisable(UARTA0_BASE);
MAP_UARTIntDisable(UARTA0_BASE, UART_INT_RX | UART_INT_TX);
/* Free the buffers */
in_buffer_.destroy();
out_buffer_.destroy();
/* Clean the port open status */
open_ = false;
g_uart0_object = NULL;
}
//------------------------------------------------------------------------------
BOOL Send_Data_uart(const char *buf, unsigned char len)
{
unsigned char send_first_byte = g_tx_buf_len;
MAP_UARTIntDisable(UART_BASE, UART_INT_TX);
while (len-- && g_tx_buf_len<UART_BUF_SZ)
{
g_tx_buf[g_tx_buf_len++] = *buf++;
}
MAP_UARTIntEnable(UART_BASE, UART_INT_TX);
if (!send_first_byte) // Если ничего до этого не отправлялось
tx_pkt_snd_one();
return !len;
}
void HardwareSerial::UARTIntHandler(void)
{
unsigned long ulInts;
long lChar;
/* Get and clear the current interrupt source(s) */
ulInts = MAP_UARTIntStatus(UART_BASE, true);
MAP_UARTIntClear(UART_BASE, ulInts);
/* Are we being interrupted because the TX FIFO has space available? */
if(ulInts & UART_INT_TX) {
/* Move as many bytes as we can into the transmit FIFO. */
primeTransmit(UART_BASE);
/* If the output buffer is empty, turn off the transmit interrupt. */
if(TX_BUFFER_EMPTY) {
MAP_UARTIntDisable(UART_BASE, UART_INT_TX);
}
}
if(ulInts & (UART_INT_RT | UART_INT_TX)) {
while(MAP_UARTCharsAvail(UART_BASE)) {
/* Read a character */
lChar = MAP_UARTCharGetNonBlocking(UART_BASE);
/* If there is space in the receive buffer, put the character
* there, otherwise throw it away. */
uint8_t volatile full = RX_BUFFER_FULL;
if(full) break;
rxBuffer[rxWriteIndex] = (unsigned char)(lChar & 0xFF);
rxWriteIndex = ((rxWriteIndex) + 1) % rxBufferSize;
/* If we wrote anything to the transmit buffer, make sure it actually
* gets transmitted. */
}
primeTransmit(UART_BASE);
MAP_UARTIntEnable(UART_BASE, UART_INT_TX);
}
}
void cc32xx_uart_early_init(int uart_no, int baud_rate) {
if (uart_no < 0) return;
uint32_t base = cc32xx_uart_get_base(uart_no);
uint32_t periph;
if (uart_no == 0) {
periph = PRCM_UARTA0;
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* UART0_RX */
} else if (uart_no == 1) {
periph = PRCM_UARTA1;
MAP_PinTypeUART(PIN_07, PIN_MODE_5); /* UART1_TX */
MAP_PinTypeUART(PIN_08, PIN_MODE_5); /* UART1_RX */
} else {
return;
}
MAP_PRCMPeripheralClkEnable(periph, PRCM_RUN_MODE_CLK);
MAP_UARTConfigSetExpClk(
base, MAP_PRCMPeripheralClockGet(periph), baud_rate,
UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE);
MAP_UARTFIFODisable(base);
MAP_UARTIntDisable(base, ~0); /* Start with ints disabled. */
}
void mgos_uart_hal_dispatch_rx_top(struct mgos_uart_state *us) {
bool recd;
struct cc32xx_uart_state *ds = (struct cc32xx_uart_state *) us->dev_data;
cs_rbuf_t *irxb = &ds->isr_rx_buf;
MAP_UARTIntDisable(ds->base, UART_RX_INTS);
recv_more:
recd = false;
cc32xx_uart_rx_bytes(ds->base, irxb);
while (irxb->used > 0 && mgos_uart_rxb_free(us) > 0) {
int num_recd = 0;
do {
uint8_t *data;
int num_to_get = MIN(mgos_uart_rxb_free(us), irxb->used);
num_recd = cs_rbuf_get(irxb, num_to_get, &data);
mbuf_append(&us->rx_buf, data, num_recd);
cs_rbuf_consume(irxb, num_recd);
us->stats.rx_bytes += num_recd;
if (num_recd > 0) recd = true;
cc32xx_uart_rx_bytes(ds->base, irxb);
} while (num_recd > 0);
}
/* If we received something during this cycle and there is buffer space
* available, "linger" for some more, maybe there's more to come. */
if (recd && mgos_uart_rxb_free(us) > 0 && us->cfg.rx_linger_micros > 0) {
/* Magic constants below are tweaked so that the loop takes at most the
* configured number of microseconds. */
int ctr = us->cfg.rx_linger_micros * 31 / 12;
// HWREG(GPIOA1_BASE + GPIO_O_GPIO_DATA + 8) = 0xFF; /* Pin 64 */
while (ctr-- > 0) {
if (MAP_UARTCharsAvail(ds->base)) {
us->stats.rx_linger_conts++;
goto recv_more;
}
}
// HWREG(GPIOA1_BASE + GPIO_O_GPIO_DATA + 8) = 0; /* Pin 64 */
}
MAP_UARTIntClear(ds->base, UART_RX_INTS);
}
/*
* @brief Initializes serial I/O.
*
* Enable the peripherals used by this example.
* Enable processor interrupts.
* Set GPIO A0 and A1 as UART pins.
* Configure the UART for 115,200, 8-N-1 operation.
* Enable the UART interrupt.
* @returns void
*/
void serialInit() {
// Enable the peripherals.
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
// Set GPIO A0 and A1 as UART pins.
MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
// Configure the UART for 230,400, 8N1 operation.
MAP_UARTConfigSetExpClk(UART0_BASE, SYSCTL_CLOCK_FREQ, SERIAL_BAUDRATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
// MAP_UARTFIFOEnable(UART0_BASE);
// // set the fifos for 1/8 empty on transmit and 3/4 full on receive
// MAP_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX7_8, UART_FIFO_RX1_8);
// Enable the UART interrupts (receive only).
MAP_UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
MAP_UARTIntDisable(UART0_BASE, UART_INT_TX);
// Enable the interrupt in the NVIC with the right priority for FreeRTOS
// MAP_IntPrioritySet(INT_UART0, SYSTEM_INTERRUPT_PRIORITY);
// MAP_IntEnable(INT_UART0);
}
static void uart_int() {
struct sj_event e = {.type = PROMPT_CHAR_EVENT, .data = NULL};
MAP_UARTIntClear(CONSOLE_UART, UART_INT_RX | UART_INT_RT);
MAP_UARTIntDisable(CONSOLE_UART, UART_INT_RX | UART_INT_RT);
osi_MsgQWrite(&s_main_queue, &e, OSI_NO_WAIT);
}
bool initializeUartChannel(uint8_t channel,
uint8_t uartPort,
uint32_t baudRate,
uint32_t cpuSpeedHz,
uint32_t flags)
{
if (channel >= UART_NUMBER_OF_CHANNELS ||
uartPort >= UART_COUNT)
{
return false;
}
if (uart2UartChannelData[uartPort] != 0)
{
return false;
}
if (!(flags & UART_FLAGS_RECEIVE) && !(flags & UART_FLAGS_SEND))
{
return false;
}
uint32_t uartBase;
uint32_t uartInterruptId;
uint32_t uartPeripheralSysCtl;
switch (uartPort)
{
#ifdef DEBUG
case UART_0:
{
uartBase = UART0_BASE;
uartInterruptId = INT_UART0;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART0;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
break;
}
#endif
case UART_1:
{
uartBase = UART1_BASE;
uartInterruptId = INT_UART1;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART1;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
ROM_GPIOPinConfigure(GPIO_PB0_U1RX);
ROM_GPIOPinConfigure(GPIO_PB1_U1TX);
ROM_GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1);
break;
}
case UART_2:
{
uartBase = UART2_BASE;
uartInterruptId = INT_UART2;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART2;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART2);
ROM_GPIOPinConfigure(GPIO_PD6_U2RX);
ROM_GPIOPinConfigure(GPIO_PD7_U2TX);
ROM_GPIOPinTypeUART(GPIO_PORTD_BASE, GPIO_PIN_6 | GPIO_PIN_7);
break;
}
case UART_3:
{
uartBase = UART3_BASE;
uartInterruptId = INT_UART3;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART3;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART3);
ROM_GPIOPinConfigure(GPIO_PC6_U3RX);
ROM_GPIOPinConfigure(GPIO_PC7_U3TX);
ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_6 | GPIO_PIN_7);
break;
}
case UART_4:
{
uartBase = UART4_BASE;
uartInterruptId = INT_UART4;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART4;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART4);
ROM_GPIOPinConfigure(GPIO_PC4_U4RX);
ROM_GPIOPinConfigure(GPIO_PC5_U4TX);
ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
break;
}
default:
{
return false;
}
}
UARTClockSourceSet(uartBase, UART_CLOCK_PIOSC);
if(!MAP_SysCtlPeripheralPresent(uartPeripheralSysCtl))
{
return false;
}
MAP_SysCtlPeripheralEnable(uartPeripheralSysCtl);
MAP_UARTConfigSetExpClk(uartBase,
cpuSpeedHz,
baudRate,
(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | UART_CONFIG_WLEN_8));
MAP_UARTFIFOLevelSet(uartBase, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
MAP_UARTIntDisable(uartBase, 0xFFFFFFFF);
if (flags & UART_FLAGS_RECEIVE)
{
MAP_UARTIntEnable(uartBase, UART_INT_RX | UART_INT_RT);
}
if (flags & UART_FLAGS_SEND)
{
MAP_UARTIntEnable(uartBase, UART_INT_TX);
}
MAP_IntEnable(uartInterruptId);
MAP_UARTEnable(uartBase);
uartChannelData[channel].base = uartBase;
uartChannelData[channel].interruptId = uartInterruptId;
uartChannelData[channel].writeBuffer.isEmpty = true;
uart2UartChannelData[uartPort] = &uartChannelData[channel];
return true;
}
STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
bool success;
// parse args
mp_arg_val_t args[MP_ARRAY_SIZE(pyb_uart_init_args)];
mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(pyb_uart_init_args), pyb_uart_init_args, args);
// set the UART configuration values
if (n_args > 1) {
self->baudrate = args[0].u_int;
switch (args[1].u_int) {
case 5:
self->config = UART_CONFIG_WLEN_5;
break;
case 6:
self->config = UART_CONFIG_WLEN_6;
break;
case 7:
self->config = UART_CONFIG_WLEN_7;
break;
case 8:
self->config = UART_CONFIG_WLEN_8;
break;
default:
nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, mpexception_value_invalid_arguments));
break;
}
// Parity
if (args[2].u_obj == mp_const_none) {
self->config |= UART_CONFIG_PAR_NONE;
} else {
self->config |= ((mp_obj_get_int(args[2].u_obj) & 1) ? UART_CONFIG_PAR_ODD : UART_CONFIG_PAR_EVEN);
}
// Stop bits
self->config |= (args[3].u_int == 1 ? UART_CONFIG_STOP_ONE : UART_CONFIG_STOP_TWO);
// Flow control
self->flowcontrol = args[4].u_int;
success = uart_init2(self);
} else {
success = uart_init(self, args[0].u_int);
}
// init UART (if it fails, something weird happened)
if (!success) {
nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_os_operation_failed));
}
// set timeouts
self->timeout = args[5].u_int;
self->timeout_char = args[6].u_int;
// setup the read buffer
m_del(byte, self->read_buf, self->read_buf_len);
self->read_buf_head = 0;
self->read_buf_tail = 0;
if (args[7].u_int <= 0) {
// no read buffer
self->read_buf_len = 0;
self->read_buf = NULL;
MAP_UARTIntDisable(self->reg, UART_INT_RX | UART_INT_RT);
} else {
// read buffer using interrupts
self->read_buf_len = args[7].u_int;
self->read_buf = m_new(byte, args[7].u_int);
}
return mp_const_none;
}
bool mgos_uart_hal_configure(struct mgos_uart_state *us,
const struct mgos_uart_config *cfg) {
uint32_t base = cc32xx_uart_get_base(us->uart_no);
if (us->uart_no == 0 && (cfg->tx_fc_type == MGOS_UART_FC_HW ||
cfg->rx_fc_type == MGOS_UART_FC_HW)) {
/* No FC on UART0, according to the TRM. */
return false;
}
MAP_UARTIntDisable(base, ~0);
uint32_t periph = (us->uart_no == 0 ? PRCM_UARTA0 : PRCM_UARTA1);
uint32_t data_cfg = 0;
switch (cfg->num_data_bits) {
case 5:
data_cfg |= UART_CONFIG_WLEN_5;
break;
case 6:
data_cfg |= UART_CONFIG_WLEN_6;
break;
case 7:
data_cfg |= UART_CONFIG_WLEN_7;
break;
case 8:
data_cfg |= UART_CONFIG_WLEN_8;
break;
default:
return false;
}
switch (cfg->parity) {
case MGOS_UART_PARITY_NONE:
data_cfg |= UART_CONFIG_PAR_NONE;
break;
case MGOS_UART_PARITY_EVEN:
data_cfg |= UART_CONFIG_PAR_EVEN;
break;
case MGOS_UART_PARITY_ODD:
data_cfg |= UART_CONFIG_PAR_ODD;
break;
}
switch (cfg->stop_bits) {
case MGOS_UART_STOP_BITS_1:
data_cfg |= UART_CONFIG_STOP_ONE;
break;
case MGOS_UART_STOP_BITS_1_5:
return false; /* Not supported */
case MGOS_UART_STOP_BITS_2:
data_cfg |= UART_CONFIG_STOP_TWO;
break;
}
MAP_UARTConfigSetExpClk(base, MAP_PRCMPeripheralClockGet(periph),
cfg->baud_rate, data_cfg);
if (cfg->tx_fc_type == MGOS_UART_FC_HW ||
cfg->rx_fc_type == MGOS_UART_FC_HW) {
/* Note: only UART1 */
uint32_t ctl = HWREG(base + UART_O_CTL);
if (cfg->tx_fc_type == MGOS_UART_FC_HW) {
ctl |= UART_CTL_CTSEN;
MAP_PinTypeUART(PIN_61, PIN_MODE_3); /* UART1_CTS */
}
if (cfg->rx_fc_type == MGOS_UART_FC_HW) {
ctl |= UART_CTL_RTSEN;
MAP_PinTypeUART(PIN_62, PIN_MODE_3); /* UART1_RTS */
}
HWREG(base + UART_O_CTL) = ctl;
}
MAP_UARTFIFOLevelSet(base, UART_FIFO_TX1_8, UART_FIFO_RX4_8);
MAP_UARTFIFOEnable(base);
return true;
}
