コード例 #1
0
ファイル: config.c プロジェクト: antonywcl/AR-5315u_PLD
void sdramc_init(void)
{
	/*
	 * Check to see if the SDRAM has already been initialized
	 * by a run control tool
	 */
	if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
		/* SDRAM chip select initialization */
		
		/* Initialize SDRAM chip select */
		MCF_SDRAMC_SDCS0 = (0
			| MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
			| MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));

	/*
	 * Basic configuration and initialization
	 */
	MCF_SDRAMC_SDCFG1 = (0
		| MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
		| MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
		| MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
		| MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
		| MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
		| MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
		| MCF_SDRAMC_SDCFG1_WTLAT(3));
	MCF_SDRAMC_SDCFG2 = (0
		| MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
		| MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
		| MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
		| MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));

            
	/*
	 * Precharge and enable write to SDMR
	 */
        MCF_SDRAMC_SDCR = (0
		| MCF_SDRAMC_SDCR_MODE_EN
		| MCF_SDRAMC_SDCR_CKE
		| MCF_SDRAMC_SDCR_DDR
		| MCF_SDRAMC_SDCR_MUX(1)
		| MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
		| MCF_SDRAMC_SDCR_PS_16
		| MCF_SDRAMC_SDCR_IPALL);            

	/*
	 * Write extended mode register
	 */
	MCF_SDRAMC_SDMR = (0
		| MCF_SDRAMC_SDMR_BNKAD_LEMR
		| MCF_SDRAMC_SDMR_AD(0x0)
		| MCF_SDRAMC_SDMR_CMD);

	/*
	 * Write mode register and reset DLL
	 */
	MCF_SDRAMC_SDMR = (0
		| MCF_SDRAMC_SDMR_BNKAD_LMR
		| MCF_SDRAMC_SDMR_AD(0x163)
		| MCF_SDRAMC_SDMR_CMD);

	/*
	 * Execute a PALL command
	 */
	MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;

	/*
	 * Perform two REF cycles
	 */
	MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
	MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;

	/*
	 * Write mode register and clear reset DLL
	 */
	MCF_SDRAMC_SDMR = (0
		| MCF_SDRAMC_SDMR_BNKAD_LMR
		| MCF_SDRAMC_SDMR_AD(0x063)
		| MCF_SDRAMC_SDMR_CMD);
				
	/*
	 * Enable auto refresh and lock SDMR
	 */
	MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
	MCF_SDRAMC_SDCR |= (0
		| MCF_SDRAMC_SDCR_REF
		| MCF_SDRAMC_SDCR_DQS_OE(0xC));
	}
}
コード例 #2
0
/*********************************************************************
* init_sdram_controller - SDRAM Controller                           *
**********************************************************************/
void init_sdram_controller(void)
{
  /* Check to see if the SDRAM has already been initialized
     by a run control tool and skip if so
   */
  if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
    return;

  /* Ensure that there is a delay from processor reset of the time recommended in
     the SDRAM data sheet (typically 100-200 microseconds) until the following
     code so that the SDRAM is ready for commands...
   */

  /* SDRAM controller configured for Double-data rate (DDR) SDRAM
     Bus width = 16 bits
     SDRAM specification:
     SDRAM clock frequency = 80.00 MHz
     CASL = 2.5
     ACTV-to-read/write delay, tRCD = 20.0 nanoseconds
     Write recovery time, tWR = 15.0 nanoseconds
     Precharge comand to ACTV command, tRP = 20.0 nanoseconds
     Auto refresh command period, tRFC = 75.0 nanoseconds
     Average periodic refresh interval, tREFI = 7.8 microseconds
   */

  /* Memory block 0 enabled - 32 MBytes at address $40000000
     Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks)
   */
  MCF_SDRAMC_SDCS0 = MCF_SDRAMC_SDCS_BASE(0x400) | MCF_SDRAMC_SDCS_CSSZ(0x18);

  /* Memory block 1 disabled */
  MCF_SDRAMC_SDCS1 = 0;

  /* Initialise SDCFG1 register with delay and timing values
     SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2
     PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3
   */
  MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_SRD2RW(0x4) |
    MCF_SDRAMC_SDCFG1_SWT2RD(0x3) |
    MCF_SDRAMC_SDCFG1_RDLAT(0x7) |
    MCF_SDRAMC_SDCFG1_ACT2RW(0x2) |
    MCF_SDRAMC_SDCFG1_PRE2ACT(0x2) |
    MCF_SDRAMC_SDCFG1_REF2ACT(0x6) | MCF_SDRAMC_SDCFG1_WTLAT(0x3);

  /* Initialise SDCFG2 register with delay and timing values
     BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7
   */
  MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BRD2PRE(0x5) |
    MCF_SDRAMC_SDCFG2_BWT2RW(0x6) |
    MCF_SDRAMC_SDCFG2_BRD2WT(0x6) | MCF_SDRAMC_SDCFG2_BL(0x7);

  /* Issue a Precharge All command */
  MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_MODE_EN |
    MCF_SDRAMC_SDCR_CKE |
    MCF_SDRAMC_SDCR_DDR |
    MCF_SDRAMC_SDCR_MUX(0x1) |
    MCF_SDRAMC_SDCR_RCNT(0x8) | MCF_SDRAMC_SDCR_PS_16 | MCF_SDRAMC_SDCR_IPALL;

  /* Write Extended Mode Register */
  MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_CMD;

  /* Write Mode Register and Reset DLL */
  MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR |
    MCF_SDRAMC_SDMR_AD(0x163) | MCF_SDRAMC_SDMR_CMD;

  /* Insert code here to pause for DLL lock time specified by memory... */

  /* Issue a second Precharge All command */
  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;

  /* Refresh sequence...
     (check the number of refreshes required by the SDRAM manufacturer)
   */
  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;

  /* Write Mode Register and clear the Reset DLL bit */
  MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR |
    MCF_SDRAMC_SDMR_AD(0x63) | MCF_SDRAMC_SDMR_CMD;

  /* Enable automatic refresh and lock SDMR */
  MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_REF |
    MCF_SDRAMC_SDCR_DQS_OE(0x8) | MCF_SDRAMC_SDCR_DQS_OE(0x4);

}
コード例 #3
0
ファイル: lowlevel_init.c プロジェクト: cwyy/barebox
/** Initialize board specific very early inits
 *
 * @note This code is not allowed to call other code - just init
 * your Chipselects and SDRAM stuff here!
 */
void board_init_lowlevel(void)
{
	/*
	 * The phyCORE-MCF548x has a 32MB or 64MB boot flash.
	 * The is a CF Card and ControlRegs on CS1 and CS2
	 */

	/* Setup SysGlue Chip-Select for user IOs */
	MCF_FBCS_CSAR2 = MCF_FBCS_CSAR_BA(CFG_XPLD_ADDRESS);

	MCF_FBCS_CSCR2 = (MCF_FBCS_CSCR_PS_16
	                  | MCF_FBCS_CSCR_AA
	                  | MCF_FBCS_CSCR_ASET(1)
	                  | MCF_FBCS_CSCR_WS(CFG_XPLD_WAIT_STATES));

	MCF_FBCS_CSMR2 = (MCF_FBCS_CSMR_BAM_16M
	                  | MCF_FBCS_CSMR_V);

	/* Setup SysGlue Chip-Select for CFCARD */
	MCF_FBCS_CSAR1 = MCF_FBCS_CSAR_BA(CFG_CFCARD_ADDRESS);

	MCF_FBCS_CSCR1 = (MCF_FBCS_CSCR_PS_16
	                  | MCF_FBCS_CSCR_AA
	                  | MCF_FBCS_CSCR_ASET(1)
	                  | MCF_FBCS_CSCR_WS(CFG_CFCARD_WAIT_STATES));

	MCF_FBCS_CSMR1 = (MCF_FBCS_CSMR_BAM_16M
	                  | MCF_FBCS_CSMR_V);

	/* Setup boot flash chip-select */
	MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS);

	MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32
	                  | MCF_FBCS_CSCR_AA
	                  | MCF_FBCS_CSCR_ASET(1)
	                  | MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES));

	MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M
	                  | MCF_FBCS_CSMR_V);

	/*
	* Check to see if the SDRAM has already been initialized
	* by a run control tool
	*/
	if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
	{
		/*
		* Basic configuration and initialization
		*/
		// 0x000002AA
		MCF_SDRAMC_SDRAMDS = (0
		                      | MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
		                      | MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
		                      | MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
		                      | MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
		                      | MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
		                     );

		// 0x0000001A
		MCF_SDRAMC_CS0CFG = (0
		                     | MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS)
		                     | MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE)
		                    );

		MCF_SDRAMC_CS1CFG = 0;
		MCF_SDRAMC_CS2CFG = 0;
		MCF_SDRAMC_CS3CFG = 0;

		// 0x73611730
		MCF_SDRAMC_SDCFG1 = (0
		                     | MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5))
		                     | MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1))
		                     | MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2))
		                     | MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
		                     | MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
		                     | MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
		                     | MCF_SDRAMC_SDCFG1_WTLAT(3)
		                    );

		// 0x46770000
		MCF_SDRAMC_SDCFG2 = (0
		                     | MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2)
		                     | MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR)
		                     | MCF_SDRAMC_SDCFG2_BRD2WT(7)
		                     | MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1)
		                    );

		/*
		* Precharge and enable write to SDMR
		*/
		// 0xE10B0002
		MCF_SDRAMC_SDCR = (0
		                   | MCF_SDRAMC_SDCR_MODE_EN
		                   | MCF_SDRAMC_SDCR_CKE
		                   | MCF_SDRAMC_SDCR_DDR
		                   | MCF_SDRAMC_SDCR_MUX(1)    // 13 x 10 x 2 ==> MUX=1
		                   | MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5))
		                   | MCF_SDRAMC_SDCR_IPALL
		                  );

		/*
		* Write extended mode register
		*/
		// 0x40010000
		MCF_SDRAMC_SDMR = (0
		                   | MCF_SDRAMC_SDMR_BNKAD_LEMR
		                   | MCF_SDRAMC_SDMR_AD(0x0)
		                   | MCF_SDRAMC_SDMR_CMD
		                  );

		/*
		* Write mode register and reset DLL
		*/
		// 0x048d0000
		MCF_SDRAMC_SDMR = (0
		                   | MCF_SDRAMC_SDMR_BNKAD_LMR
		                   | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD)
		                   | MCF_SDRAMC_SDMR_CMD
		                  );

		/*
		* Execute a PALL command
		*/
		// 0xE10B0002
		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;

		/*
		* Perform two REF cycles
		*/
		// 0xE10B0004
		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;

		/*
		* Write mode register and clear reset DLL
		*/
		// 0x008D0000
		MCF_SDRAMC_SDMR = (0
		                   | MCF_SDRAMC_SDMR_BNKAD_LMR
		                   | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD)
		                   | MCF_SDRAMC_SDMR_CMD
		                  );

		/*
		* Enable auto refresh and lock SDMR
		*/
		// 0x610B0000
		MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;

		// 0x710B0F00
		MCF_SDRAMC_SDCR |= (0
		                    | MCF_SDRAMC_SDCR_REF
		                    | MCF_SDRAMC_SDCR_DQS_OE(0xF)
		                   );
	}
}