static enum uart yam_check_uart(unsigned int iobase)
{
unsigned char b1, b2, b3;
enum uart u;
enum uart uart_tab[] =
{c_uart_16450, c_uart_unknown, c_uart_16550, c_uart_16550A};
b1 = inb(MCR(iobase));
outb(b1 | 0x10, MCR(iobase)); /* loopback mode */
b2 = inb(MSR(iobase));
outb(0x1a, MCR(iobase));
b3 = inb(MSR(iobase)) & 0xf0;
outb(b1, MCR(iobase)); /* restore old values */
outb(b2, MSR(iobase));
if (b3 != 0x90)
return c_uart_unknown;
inb(RBR(iobase));
inb(RBR(iobase));
outb(0x01, FCR(iobase)); /* enable FIFOs */
u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
if (u == c_uart_16450) {
outb(0x5a, SCR(iobase));
b1 = inb(SCR(iobase));
outb(0xa5, SCR(iobase));
b2 = inb(SCR(iobase));
if ((b1 != 0x5a) || (b2 != 0xa5))
u = c_uart_8250;
}
return u;
}
void serial_cdev_exit(void)
{
int minors;
minors = info[0] + info[1];
// Eliberez toate resursele
if (info[0])
{
//printk(LOG_LEVEL "cdev_del %d", 0);
outb(0x0, MCR(COM1_BASEPORT));
outb(0x0, IER(COM1_BASEPORT));
free_irq(COM1_IRQ, &uart[0]);
release_region(COM1_BASEPORT, COM_PORTS);
cdev_del(&uart[0].cdev);
}
if (info[1])
{
//printk(LOG_LEVEL "cdev_del %d", 1);
outb(0x0, MCR(COM2_BASEPORT));
outb(0x0, IER(COM2_BASEPORT));
free_irq(COM2_IRQ, &uart[1]);
release_region(COM2_BASEPORT, COM_PORTS);
cdev_del(&uart[1].cdev);
}
unregister_chrdev_region(MKDEV(major, 0), minors);
}
void serial_setbrg (void)
{
unsigned int quot = 0;
int uart = CONFIG_SYS_IXP425_CONSOLE;
if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0))
quot = SERIAL_CLOCK / gd->baudrate;
else
hang ();
IER(uart) = 0; /* Disable for now */
FCR(uart) = 0; /* No fifos enabled */
/* set baud rate */
LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
DLL(uart) = quot & 0xff;
DLH(uart) = quot >> 8;
LCR(uart) = LCR_WLS0 | LCR_WLS1;
#ifdef CONFIG_SERIAL_RTS_ACTIVE
MCR(uart) = MCR_RTS; /* set RTS active */
#else
MCR(uart) = 0; /* set RTS inactive */
#endif
IER(uart) = IER_UUE;
}
static void
update_theta(void)
{
int i, j, x, y, z;
/* Update all cell representatives */
for (i = 0; i < n; ++i) {
/* Look for the start of an orbit */
if (i >= gamma[i]) continue;
/* Find the cell rep for the two elements */
for (x = i; x != theta[x]; x = theta[x]);
for (y = gamma[i]; y != theta[y]; y = theta[y]);
/* Pick the cell with the smaller representative */
z = (x < y) ? x : y;
/* Update the old root's cell representatives */
theta[x] = theta[y] = z;
}
/* Clear out last automorphism if we've already saved max */
if (saved == max_saved) {
--saved;
BWIPE(FIX(saved), n);
BWIPE(MCR(saved), n);
}
/* Look for orbits in gamma and update fix and mcr */
for (i = 0; i < n; ++i) {
/* Find the start of an orbit, and save it as an mcr */
if (BISSET(bit_contents, i)) continue;
BSET(bit_contents, i);
BSET(MCR(saved), i);
/* If the element is fixed, save as fixed and continue */
if (gamma[i] == i) {
BSET(FIX(saved), i);
continue;
}
/* Find all other elements in the orbit */
for (j = gamma[i]; j != i; j = gamma[j]) {
BSET(bit_contents, j);
}
}
/* Clean up */
BWIPE(bit_contents, n);
++saved;
}
void data_cache_clean()
{
mem_dsb();
mem_dmb();
MCR(15, 0, 7, 10, 0, 0);
}
static void Ap15CorePerfMonStart(NvU32* pEventList, NvU32* pEventListSize)
{
NvU32 RegValue, Event0, Event1;
// Just return maximum monitored events if no input list, otherwise
// get both events ready (set the same if only one specified)
if (*pEventListSize == 0)
{
*pEventListSize = NVRM_AP15_MONITORED_EVENTS_MAX;
return;
}
Event0 = Event1 = pEventList[0];
if (*pEventListSize >= NVRM_AP15_MONITORED_EVENTS_MAX)
{
Event1 = pEventList[1];
*pEventListSize = NVRM_AP15_MONITORED_EVENTS_MAX;
}
// Reset, clear overflow flags and enable 3 performance counters:
// total cycle counter and 2 event counters
RegValue =
NV_DRF_NUM(AP15_CP15, PMNC, ENABLE, 1) |
NV_DRF_NUM(AP15_CP15, PMNC, EVENT_CNTS_RESET, 1) |
NV_DRF_NUM(AP15_CP15, PMNC, CYCLE_CNT_RESET, 1) |
NV_DRF_NUM(AP15_CP15, PMNC, CYCLE_CNT_OV, 1) |
NV_DRF_NUM(AP15_CP15, PMNC, EVENT0_CNT_OV, 1) |
NV_DRF_NUM(AP15_CP15, PMNC, EVENT1_CNT_OV, 1) |
NV_DRF_NUM(AP15_CP15, PMNC, EVENT0, Event0) |
NV_DRF_NUM(AP15_CP15, PMNC, EVENT1, Event1);
MCR(p15, 0, RegValue, c15, c12, 0);
}
static void uart_init_line(int port, unsigned long baud)
{
int i, baudconst;
switch (baud) {
case 115200:
baudconst = 1;
break;
case 57600:
baudconst = 2;
break;
case 38400:
baudconst = 3;
break;
case 19200:
baudconst = 6;
break;
case 9600:
default:
baudconst = 12;
break;
}
outb(0x87, LCR(port));
outb(0x00, DLM(port));
outb(baudconst, DLL(port));
outb(0x07, LCR(port));
outb(0x0f, MCR(port));
for (i = 10; i > 0; i--) {
if (inb(LSR(port)) == (unsigned int) 0)
break;
inb(RBR(port));
}
}
static void
check_export_pmu(void)
{
#ifdef CONFIG_EXPORT_PMU_USER
/* Export performance counters */
uint32_t v;
v = PMUSERENR_ENABLE;
MCR(PMUSERENR, v);
/* enable user-level pmu event counter if we're in secure mode */
if (!(readDscrCp() & DBGDSCR_SECURE_MODE_DISABLED)) {
MRC(DBGSDER, v);
v |= DBGSDER_ENABLE_SECURE_USER_NON_INVASIVE_DEBUG;
MCR(DBGSDER, v);
}
#endif
}
static void fpga_reset(int iobase)
{
outb(0, IER(iobase));
outb(LCR_DLAB | LCR_BIT5, LCR(iobase));
outb(1, DLL(iobase));
outb(0, DLM(iobase));
outb(LCR_BIT5, LCR(iobase));
inb(LSR(iobase));
inb(MSR(iobase));
/* turn off FPGA supply voltage */
outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));
delay(100);
/* turn on FPGA supply voltage again */
outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));
delay(100);
}
static void
check_export_pmu(void)
{
#ifdef CONFIG_EXPORT_PMU_USER
/* Export performance counters */
uint32_t v;
v = PMUSERENR_ENABLE;
MCR(PMUSERENR, v);
#endif
}
static void
check_export_arch_timer(void)
{
uint32_t v;
MRC(CNTKCTL, v);
#ifdef CONFIG_EXPORT_PCNT_USER
v |= CNTKCTL_PL0PCTEN;
#endif
#ifdef CONFIG_EXPORT_VCNT_USER
v |= CNTKCTL_PL0VCTEN;
#endif
MCR(CNTKCTL, v);
}
static inline void ser12_tx(struct net_device *dev, struct baycom_state *bc)
{
/* one interrupt per channel bit */
ser12_set_divisor(dev, 12);
/*
* first output the last bit (!) then call HDLC transmitter,
* since this may take quite long
*/
outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr));
if (bc->modem.shreg <= 1)
bc->modem.shreg = 0x10000 | hdlcdrv_getbits(&bc->hdrv);
bc->modem.ser12.tx_bit = !(bc->modem.ser12.tx_bit ^
(bc->modem.shreg & 1));
bc->modem.shreg >>= 1;
}
static void
orbit_prune(void)
{
int i, j, good;
/* Start with a completely set bit vector */
for (j = 0; j < BSIZE(n); ++j) {
bit_contents[j] = ~0;
}
/* Find the mcr's of permutations that fix this node */
for (i = 0; i < saved; ++i) {
/* Make sure we're a superset */
for (j = 0, good = 1; good && j < BSIZE(n); ++j) {
if (bit_fixed[j] & ~FIX(i)[j]) good = 0;
}
if (!good) continue;
/* The automorphism fixes this node, so update mcr */
for (j = 0; j < BSIZE(n); ++j) {
bit_contents[j] &= MCR(i)[j];
}
}
/* Point to the start of the target cell */
target = i = start[lev];
target_min = n+1;
/* Do some orbit pruning */
do {
++i;
/* If we have a new candidate for minimum... */
if ((lab[i] > fixed[lev]) && (lab[i] < target_min)) {
/* Make it minimum if it is an mcr */
if (BISSET(bit_contents, lab[i])) {
target = i; target_min = lab[i];
}
}
/* Keep going until the end of the cell */
} while (ptn[i] > lev);
/* Clear the bit vector */
BWIPE(bit_contents, n);
}
static int fpga_write(int iobase, unsigned char wrd)
{
unsigned char bit;
int k;
unsigned long timeout = jiffies + HZ / 10;
for (k = 0; k < 8; k++) {
bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR;
outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase));
wrd <<= 1;
outb(0xfc, THR(iobase));
while ((inb(LSR(iobase)) & LSR_TSRE) == 0)
if (time_after(jiffies, timeout))
return -1;
}
return 0;
}
static int do_requests(int baseport, int irq, int index, int minor)
{
int err;
atomic_set(&uart[index].read_ready, 0);
atomic_set(&uart[index].write_ready, 0);
uart[index].read = 0;
uart[index].write = 0;
uart[index].base_port = baseport;
cdev_init(&uart[index].cdev, &serial_fops);
init_waitqueue_head(&uart[index].wq_reads);
init_waitqueue_head(&uart[index].wq_writes);
if ((err = cdev_add(&uart[index].cdev, MKDEV(major, minor), 1)))
{
//printk(LOG_LEVEL "cdev_init %d failed", minor);
return err;
}
if (request_region(baseport, COM_PORTS, MODULE_NAME) == NULL)
{
//printk(LOG_LEVEL "request_region failed for COM1");
return -EINVAL;
}
err = request_irq(irq, serial_interrupt_handle, IRQF_SHARED, MODULE_NAME,
&uart[index]);
if (err)
{
//printk(LOG_LEVEL "ERROR: %s: error %d\n", "request_irq", err);
return err;
}
// Enable FIFO cu 14 octeti
outb(0xc7, FCR(baseport));
// Enable interrupts
outb(0x08, MCR(baseport));
outb(0x01, IER(baseport));
//printk(LOG_LEVEL "index %d, baseport %d, irq %d, minor %d", index, baseport, irq, minor);
return 0;
}
static void yam_set_uart(struct net_device *dev)
{
struct yam_port *yp = netdev_priv(dev);
int divisor = 115200 / yp->baudrate;
outb(0, IER(dev->base_addr));
outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr));
outb(divisor, DLL(dev->base_addr));
outb(0, DLM(dev->base_addr));
outb(LCR_BIT8, LCR(dev->base_addr));
outb(PTT_OFF, MCR(dev->base_addr));
outb(0x00, FCR(dev->base_addr));
/* Flush pending irq */
inb(RBR(dev->base_addr));
inb(MSR(dev->base_addr));
/* Enable rx irq */
outb(ENABLE_RTXINT, IER(dev->base_addr));
}
static int yam_close(struct net_device *dev)
{
struct sk_buff *skb;
struct yam_port *yp = (struct yam_port *) dev->priv;
if (!dev || !yp)
return -EINVAL;
/*
* disable interrupts
*/
outb(0, IER(dev->base_addr));
outb(1, MCR(dev->base_addr));
/* Remove IRQ handler if last */
free_irq(dev->irq,dev);
release_region(dev->base_addr, YAM_EXTENT);
netif_stop_queue(dev);
while ((skb = skb_dequeue(&yp->send_queue)))
dev_kfree_skb(skb);
printk(KERN_INFO "%s: close yam at iobase 0x%lx irq %u\n",
yam_drvname, dev->base_addr, dev->irq);
return 0;
}
static void ptt_off(struct net_device *dev)
{
outb(PTT_OFF, MCR(dev->base_addr));
}
static void Ap15CorePerfMonDisable(void)
{
// Disable all performance counters
NvU32 RegValue = NV_DRF_NUM(AP15_CP15, PMNC, ENABLE, 0);
MCR(p15, 0, RegValue, c15, c12, 0);
}
/**
DONT_TRANSLATE
*/
void
resetTimer(void)
{
MCR(CNTV_TVAL, TIMER_RELOAD_VAL);
MCR(CNTV_CTL, (1 << 0));
}
/**
DONT_TRANSLATE
*/
void
resetTimer(void)
{
MCR(CNTV_TVAL, TIMER_TICKS);
MCR(CNTV_CTL, (1 << 0));
}
void cache_TLB_flush()
{
MCR(15, 0,8, 7, 0, 0);
}
void data_cache_clean_va(v_addr_t v_addr)
{
MCR(15, 0, 7, 10, 1, v_addr);
}
