void XCore_init(MCRegisterInfo *MRI)
{
/*
InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC,
XCoreMCRegisterClasses, 2,
XCoreRegUnitRoots,
16,
XCoreRegDiffLists,
XCoreRegStrings,
XCoreSubRegIdxLists,
1,
XCoreSubRegIdxRanges,
XCoreRegEncodingTable);
*/
MCRegisterInfo_InitMCRegisterInfo(MRI, XCoreRegDesc, 17,
0, 0,
XCoreMCRegisterClasses, 2,
0, 0,
XCoreRegDiffLists,
0,
XCoreSubRegIdxLists, 1,
0);
}
void Mips_init(MCRegisterInfo *MRI)
{
// InitMCRegisterInfo(MipsRegDesc, 317,
// RA, PC,
// MipsMCRegisterClasses, 34,
// MipsRegUnitRoots, 196,
// MipsRegDiffLists,
// MipsRegStrings,
// MipsSubRegIdxLists, 12,
// MipsSubRegIdxRanges, MipsRegEncodingTable);
MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 317,
0, 0,
MipsMCRegisterClasses, 34,
0, 0,
MipsRegDiffLists,
0,
MipsSubRegIdxLists, 12,
0);
}
void Sparc_init(MCRegisterInfo *MRI)
{
/*
InitMCRegisterInfo(SparcRegDesc, 119, RA, PC,
SparcMCRegisterClasses, 8,
SparcRegUnitRoots,
86,
SparcRegDiffLists,
SparcRegStrings,
SparcSubRegIdxLists,
7,
SparcSubRegIdxRanges,
SparcRegEncodingTable);
*/
MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119,
0, 0,
SparcMCRegisterClasses, 8,
0, 0,
SparcRegDiffLists,
0,
SparcSubRegIdxLists, 7,
0);
}
