void gl3_disable(void) { struct drm_psb_private *dev_priv = (struct drm_psb_private *) gpDrmDevice->dev_private; PSB_DEBUG_ENTRY("gl3_disable called on platform %x\n", dev_priv->platform_rev_id); if (!ospm_power_using_hw_begin(OSPM_GRAPHICS_ISLAND, true)) return; MDFLD_GL3_WRITE(MDFLD_GL3_DISABLE_CACHE, MDFLD_GL3_CONTROL); PSB_DEBUG_GENERAL("gl3 cache disabled with mask %x\n", MDFLD_GL3_DISABLE_CACHE); ospm_power_using_hw_end(OSPM_GRAPHICS_ISLAND); }
void gl3_reset(void) { struct drm_psb_private *dev_priv = (struct drm_psb_private *) gpDrmDevice->dev_private; PSB_DEBUG_ENTRY("gl3_reset called on platform %x\n", dev_priv->platform_rev_id); if (!ospm_power_using_hw_begin(OSPM_GRAPHICS_ISLAND, true)) return; // Reset the cache MDFLD_GL3_WRITE(MDFLD_GL3_SOFT_RESET_ENABLE, MDFLD_GL3_G_CONTROL); PSB_DEBUG_GENERAL("gl3 cache soft reset with mas %x\n", MDFLD_GL3_SOFT_RESET_ENABLE); ospm_power_using_hw_end(OSPM_GRAPHICS_ISLAND); }
static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData) { IMG_UINT32 ui32BaseAddr = 0; IMG_UINT32 ui32IRQ = 0; #if defined(SGX_FEATURE_HOST_PORT) IMG_UINT32 ui32HostPortAddr = 0; #endif SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; #if defined(SUPPORT_EXTERNAL_SYSTEM_CACHE) struct drm_psb_private *dev_priv = (struct drm_psb_private *) gpDrmDevice->dev_private; #endif ui32BaseAddr = OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, POULSBO_ADDR_RANGE_INDEX); #if defined(SGX_FEATURE_HOST_PORT) ui32HostPortAddr = OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, POULSBO_HP_ADDR_RANGE_INDEX); #endif if (OSPCIIRQ(psSysSpecData->hSGXPCI, &ui32IRQ) != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR,"SysLocateDevices: Couldn't get IRQ")); return PVRSRV_ERROR_INVALID_DEVICE; } PVR_TRACE(("ui32BaseAddr: %08X", ui32BaseAddr)); #if defined(SGX_FEATURE_HOST_PORT) PVR_TRACE(("ui32HostPortAddr: %08X", ui32HostPortAddr)); #endif PVR_TRACE(("IRQ: %d", ui32IRQ)); gsSGXDeviceMap.ui32Flags = 0x0; gsSGXDeviceMap.ui32IRQ = ui32IRQ; #if defined(SUPPORT_DRI_DRM_EXT) gsSGXDeviceMap.sRegsSysPBase.uiAddr = ui32BaseAddr + SGX_REGS_OFFSET; #else gsSGXDeviceMap.sRegsSysPBase.uiAddr = ui32BaseAddr + SGX_REGS_OFFSET; #endif gsSGXDeviceMap.sRegsCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sRegsSysPBase); gsSGXDeviceMap.ui32RegsSize = SGX_REG_SIZE; #if defined(SGX_FEATURE_HOST_PORT) gsSGXDeviceMap.ui32Flags = SGX_HOSTPORT_PRESENT; gsSGXDeviceMap.sHPSysPBase.uiAddr = ui32HostPortAddr; gsSGXDeviceMap.sHPCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sHPSysPBase); gsSGXDeviceMap.ui32HPSize = SYS_SGX_HP_SIZE; #endif #if defined(MRST_SLAVEPORT) gsSGXDeviceMap.sSPSysPBase.uiAddr = ui32BaseAddr + MRST_SGX_SP_OFFSET; gsSGXDeviceMap.sSPCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sSPSysPBase); gsSGXDeviceMap.ui32SPSize = SGX_SP_SIZE; #endif gsSGXDeviceMap.sLocalMemSysPBase.uiAddr = 0; gsSGXDeviceMap.sLocalMemDevPBase.uiAddr = 0; gsSGXDeviceMap.sLocalMemCpuPBase.uiAddr = 0; gsSGXDeviceMap.ui32LocalMemSize = 0; #if defined(SUPPORT_EXTERNAL_SYSTEM_CACHE) gsSGXDeviceMap.sExtSysCacheRegsDevPBase.uiAddr = SYS_EXT_SYS_CACHE_GBL_INV_REG_OFFSET; gsSGXDeviceMap.ui32ExtSysCacheRegsSize = SGX_EXT_SYSTEM_CACHE_REGS_SIZE; MDFLD_GL3_WRITE(gsSGXDeviceMap.sExtSysCacheRegsDevPBase.uiAddr, MDFLD_GL3_USE_WRT_INVAL); #endif #if !defined(NO_HARDWARE) { IMG_SYS_PHYADDR sPoulsboRegsCpuPBase; sPoulsboRegsCpuPBase.uiAddr = ui32BaseAddr + POULSBO_REGS_OFFSET; gsPoulsboRegsCPUVaddr = OSMapPhysToLin(SysSysPAddrToCpuPAddr(sPoulsboRegsCpuPBase), POULSBO_REG_SIZE, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, IMG_NULL); sPoulsboRegsCpuPBase.uiAddr = ui32BaseAddr + POULSBO_DISPLAY_REGS_OFFSET; gsPoulsboDisplayRegsCPUVaddr = OSMapPhysToLin(SysSysPAddrToCpuPAddr(sPoulsboRegsCpuPBase), POULSBO_DISPLAY_REG_SIZE, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, IMG_NULL); } #endif #if defined(PDUMP) { static IMG_CHAR pszPDumpDevName[] = "SGXMEM"; gsSGXDeviceMap.pszPDumpDevName = pszPDumpDevName; } #endif return PVRSRV_OK; }