static u32 cursor_blend_value(int cursor_id, enum mdp_mixer_stage_id val) { switch (cursor_id) { case 0: return MDP5_CTL_LAYER_EXT_REG_CURSOR0(val); case 1: return MDP5_CTL_LAYER_EXT_REG_CURSOR1(val); default: return 0; } }
static u32 mdp_ctl_blend_ext_mask(enum mdp5_pipe pipe, enum mdp_mixer_stage_id stage) { if (stage < STAGE6 && (pipe != SSPP_CURSOR0 && pipe != SSPP_CURSOR1)) return 0; switch (pipe) { case SSPP_VIG0: return MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3; case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3; case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3; case SSPP_RGB0: return MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3; case SSPP_RGB1: return MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3; case SSPP_RGB2: return MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3; case SSPP_DMA0: return MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3; case SSPP_DMA1: return MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3; case SSPP_VIG3: return MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3; case SSPP_RGB3: return MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3; case SSPP_CURSOR0: return MDP5_CTL_LAYER_EXT_REG_CURSOR0(stage); case SSPP_CURSOR1: return MDP5_CTL_LAYER_EXT_REG_CURSOR1(stage); default: return 0; } }