static void intel_dsi_enable(struct intel_encoder *encoder) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); int pipe = intel_crtc->pipe; u32 temp; DRM_DEBUG_KMS("\n"); if (is_cmd_mode(intel_dsi)) I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); else { msleep(20); /* XXX */ dpi_send_cmd(intel_dsi, TURN_ON); msleep(100); /* assert ip_tg_enable signal */ temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; temp = temp | intel_dsi->port_bits; I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); POSTING_READ(MIPI_PORT_CTRL(pipe)); } if (intel_dsi->dev.dev_ops->enable) intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); }
static void intel_dsi_pre_enable(struct intel_encoder *encoder) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); int pipe = intel_crtc->pipe; DRM_DEBUG_KMS("\n"); intel_enable_dsi_pll(intel_dsi); if (is_cmd_mode(intel_dsi)) { /* XXX: Implement me */ I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); } else { intel_dsi->hs = 0; dpi_send_cmd(intel_dsi, TURN_ON); usleep_range(1000, 1500); if (intel_dsi->dev.dev_ops->enable) intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); intel_dsi_port_enable(encoder); } }
static void intel_dsi_enable(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); int pipe = intel_crtc->pipe; u32 temp; DRM_DEBUG_KMS("\n"); temp = I915_READ(MIPI_DEVICE_READY(pipe)); if ((temp & DEVICE_READY) == 0) { temp &= ~ULPS_STATE_MASK; I915_WRITE(MIPI_DEVICE_READY(pipe), temp | DEVICE_READY); } else if (temp & ULPS_STATE_MASK) { temp &= ~ULPS_STATE_MASK; I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_EXIT); /* * We need to ensure that there is a minimum of 1 ms time * available before clearing the UPLS exit state. */ msleep(2); I915_WRITE(MIPI_DEVICE_READY(pipe), temp); } if (is_cmd_mode(intel_dsi)) I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); if (is_vid_mode(intel_dsi)) { msleep(20); /* XXX */ dpi_send_cmd(intel_dsi, TURN_ON); msleep(100); /* assert ip_tg_enable signal */ temp = I915_READ(MIPI_PORT_CTRL(pipe)); I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); POSTING_READ(MIPI_PORT_CTRL(pipe)); } intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); }
static void intel_dsi_pre_enable(struct intel_encoder *encoder) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); int pipe = intel_crtc->pipe; bool is_dsi; u32 temp; DRM_DEBUG_KMS("\n"); is_dsi = intel_pipe_has_type(encoder->base.crtc, INTEL_OUTPUT_DSI); intel_enable_dsi_pll(intel_dsi); printk("====>DLP3430 debug 2.20.\n"); if (is_cmd_mode(intel_dsi)) { /* XXX: Implement me */ I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); } else { intel_dsi->hs = 1; dpi_send_cmd(intel_dsi, TURN_ON); usleep_range(1000, 1500); if (intel_dsi->dev.dev_ops->enable) intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); temp = I915_READ(MIPI_PORT_CTRL(pipe)); temp = temp | intel_dsi->port_bits; if (is_dsi && intel_crtc->config.dither) temp |= DITHERING_ENABLE; I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); usleep_range(2000, 2500); } }
static void intel_dsi_mode_set(struct intel_encoder *intel_encoder) { struct drm_encoder *encoder = &intel_encoder->base; struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); int pipe = intel_crtc->pipe; unsigned int bpp = intel_crtc->config.pipe_bpp; struct drm_display_mode *adjusted_mode = &intel_crtc->config.adjusted_mode; u32 val; intel_dsi_device_ready(intel_encoder); I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); dsi_config(encoder); I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); /* in terms of low power clock */ I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), \ intel_dsi->hs_to_lp_count); I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), ((u32)intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT) | (intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT)); if (is_vid_mode(intel_dsi)) { I915_WRITE(MIPI_DPI_RESOLUTION(pipe), (adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT) | (adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT)); set_dsi_timings(encoder, adjusted_mode); if (intel_dsi->video_mode_type == DSI_VIDEO_BURST) { I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), txbyteclkhs(adjusted_mode->htotal, bpp, intel_dsi->lane_count) + 1); } else { I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), txbyteclkhs(adjusted_mode->vtotal * adjusted_mode->htotal, bpp, intel_dsi->lane_count) + 1); } } else { val = intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT | intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT | intel_dsi->data_width; I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), txbyteclkhs(adjusted_mode->hdisplay * adjusted_mode->vdisplay, bpp, intel_dsi->lane_count) + 1); I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); } I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); val = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); val &= ~VID_MODE_FORMAT_MASK; I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); #if 0 //in dual display config, dsi 0 is not init. so this function may not //be called with pipe0. set this flag for pipe0 so that pipe b can work #ifdef BYT_DUAL_MIPI_DSI if(pipe != 0) { I915_WRITE_BITS(MIPI_PORT_CTRL(0), LP_OUTPUT_HOLD, LP_OUTPUT_HOLD); usleep_range(1000, 1500); } #endif #endif if (intel_dsi->dev.dev_ops->send_otp_cmds) intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); set_dsi_timings(encoder, adjusted_mode); /* Some panels might have resolution which is not a multiple of * 64 like 1366 x 768. Enable RANDOM resolution support for such * panels by default */ I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_type | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION); val = 0; if (intel_dsi->eotp_pkt == 0) val |= EOT_DISABLE; if (intel_dsi->clock_stop) val |= CLOCKSTOP; I915_WRITE(MIPI_EOT_DISABLE(pipe), val); val = intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT | intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT | intel_dsi->pixel_format; I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); I915_WRITE(MIPI_INTR_STAT(pipe), 0xFFFFFFFF); /* Max packet return size limits the size of returning * packet so that host processor can prevent buffer overflow * condition when receiving data from peripheral. DCS read * need this to be set.*/ I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 0xff); }