static void virge_chipset_accel_shutdown (virge_chipset_io_t *virge_io) {
kgi_u_t foo;
if (!(CRT_IN8(virge_io, CRT_EXTMISCCONTROL1) & CR66_ENBL_ENH))
return; /* S3D Engine already disabled.*/
virge_chipset_accel_sync (virge_io);
/* Reset S3d Engine */
MMIO_OUT32(0x00008000, SUBSYSTEM_CONTROL);
MMIO_OUT32(0x00004000, SUBSYSTEM_CONTROL);
/* Wait till S3d Engine is ready. */
for (foo = MUCH; --foo && !(MMIO_IN32(SUBSYSTEM_CONTROL) & 0x02000););
if (0 == foo) KRN_DEBUG (0,"ViRGE: S3D Engine reset failed.");
}
static inline void virge_chipset_accel_sync(virge_chipset_io_t *virge_io)
{
kgi_u32_t foo;
KRN_DEBUG(2, "virge_chipset_accel_sync()");
/* Wait for S3d Engine */
if (CRT_IN8(virge_io, CRT_EXTMISCCONTROL1) & CR66_ENBL_ENH) {
for (foo=MUCH;--foo && !(MMIO_IN32(SUBSYSTEM_STATUS)& SSS_S3D_ENG););
if (!foo) KRN_DEBUG (1,"ViRGE: S3d Engine seems to be crashed.");
}
return;
}
int
Permedia3MemorySizeDetect(ScrnInfoPtr pScrn)
{
GLINTPtr pGlint = GLINTPTR (pScrn);
CARD32 size = 0, temp, temp1, temp2, i;
/* We can map 64MB, as that's the size of the Permedia3 aperture
* regardless of memory configuration */
pGlint->FbMapSize = 64*1024*1024;
#ifndef XSERVER_LIBPCIACCESS
/* Mark as VIDMEM_MMIO to avoid write-combining while detecting memory */
pGlint->FbBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO,
pGlint->PciTag, pGlint->FbAddress, pGlint->FbMapSize);
#else
{
void** result = (void**)&pGlint->FbBase;
int err = pci_device_map_range(pGlint->PciInfo,
pGlint->FbAddress,
pGlint->FbMapSize,
PCI_DEV_MAP_FLAG_WRITABLE,
result);
if (err)
return FALSE;
}
#endif
if (pGlint->FbBase == NULL)
return 0;
temp = GLINT_READ_REG(PM3MemBypassWriteMask);
GLINT_SLOW_WRITE_REG(0xffffffff, PM3MemBypassWriteMask);
/* The Permedia3 splits up memory, and even replicates it. Grrr.
* So that each 32MB appears at offset 0, and offset 32, unless
* there's really 64MB attached to the chip.
* So, 16MB appears at offset 0, nothing between 16-32, then it re-appears
* at offset 32.
* This below is to detect the cases of memory combinations
*/
/* Test first 32MB */
for(i=0;i<32;i++) {
/* write test pattern */
MMIO_OUT32(pGlint->FbBase, i*1024*1024, i*0x00345678);
mem_barrier();
temp1 = MMIO_IN32(pGlint->FbBase, i*1024*1024);
/* Let's check for wrapover, write will fail at 16MB boundary */
if (temp1 == (i*0x00345678))
size = i;
else
break;
}
/* Ok, we're satisfied we've got 32MB, let's test the second lot */
if ((size + 1) == i) {
for(i=0;i<32;i++) {
/* Clear first 32MB */
MMIO_OUT32(pGlint->FbBase, i*1024*1024, 0);
}
mem_barrier();
for(i=32;i<64;i++) {
/* write test pattern */
MMIO_OUT32(pGlint->FbBase, i*1024*1024, i*0x00345678);
mem_barrier();
temp1 = MMIO_IN32(pGlint->FbBase, i*1024*1024);
temp2 = MMIO_IN32(pGlint->FbBase, (i-32)*1024*1024);
/* Let's check for wrapover */
if ( (temp1 == (i*0x00345678)) && (temp2 == 0) )
size = i;
else
break;
}
}
GLINT_SLOW_WRITE_REG(temp, PM3MemBypassWriteMask);
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)pGlint->FbBase,
pGlint->FbMapSize);
#else
pci_device_unmap_range(pGlint->PciInfo, pGlint->FbBase, pGlint->FbMapSize);
#endif
pGlint->FbBase = NULL;
pGlint->FbMapSize = 0;
return ( (size+1) * 1024 );
}
int DrawTriangle( tridentContextPtr tmesa)
{
unsigned char *MMIO = tmesa->tridentScreen->mmio.map;
dmaBufRec clr;
printf("DRAW TRI\n");
Init3D(tmesa);
printf("ENGINE STATUS 0x%x\n",MMIO_IN32(MMIO, 0x2800));
MMIO_OUT32(MMIO, 0x002800, 0x00000000 );
#if 0
MMIO_OUT32(MMIO, 0x002368 , MMIO_IN32(MMIO,0x002368)|1 );
#endif
MMIO_OUT32(MMIO, 0x002C00 , 0x00000014 );
#if 0
MMIO_OUT32(MMIO, 0x002C04 , 0x0A8004C0 );
#else
MMIO_OUT32(MMIO, 0x002C04 , 0x0A8000C0 );
#endif
#if 0
MMIO_OUT32(MMIO, 0x002C08 , 0x00000000 );
MMIO_OUT32(MMIO, 0x002C0C , 0xFFCCCCCC );
MMIO_OUT32(MMIO, 0x002C10 , 0x3F800000 );
MMIO_OUT32(MMIO, 0x002C14 , 0x3D0D3DCB );
MMIO_OUT32(MMIO, 0x002C2C , 0x70000000 );
MMIO_OUT32(MMIO, 0x002C24 , 0x00202C00 );
MMIO_OUT32(MMIO, 0x002C28 , 0xE0002500 );
MMIO_OUT32(MMIO, 0x002C30 , 0x00000000 );
MMIO_OUT32(MMIO, 0x002C34 , 0xE0000000 );
MMIO_OUT32(MMIO, 0x002C38 , 0x00000000 );
#endif
MMIO_OUT32(MMIO, 0x002C50 , 0x00000000 );
MMIO_OUT32(MMIO, 0x002C54 , 0x0C320C80 );
MMIO_OUT32(MMIO, 0x002C50 , 0x00000000 );
MMIO_OUT32(MMIO, 0x002C54 , 0x0C320C80 );
MMIO_OUT32(MMIO, 0x002C80 , 0x20008258 );
MMIO_OUT32(MMIO, 0x002C84 , 0x20000320 );
MMIO_OUT32(MMIO, 0x002C94 , 0xFFFFFFFF );
#if 0
MMIO_OUT32(MMIO, 0x002D00 , 0x00009009 );
MMIO_OUT32(MMIO, 0x002D38 , 0x00000000 );
MMIO_OUT32(MMIO, 0x002D94 , 0x20002000 );
MMIO_OUT32(MMIO, 0x002D50 , 0xf0000000 );
MMIO_OUT32(MMIO, 0x002D80 , 0x24002000 );
MMIO_OUT32(MMIO, 0x002D98 , 0x81000000 );
MMIO_OUT32(MMIO, 0x002DB0 , 0x81000000 );
MMIO_OUT32(MMIO, 0x002DC8 , 0x808000FF );
MMIO_OUT32(MMIO, 0x002DD4 , 0x02000200 );
MMIO_OUT32(MMIO, 0x002DD8 , 0x02000200 );
MMIO_OUT32(MMIO, 0x002D30 , 0x02092400 );
MMIO_OUT32(MMIO, 0x002D04 , 0x00102120 );
MMIO_OUT32(MMIO, 0x002D08 , 0xFFFFFFFF );
MMIO_OUT32(MMIO, 0x002D0C , 0xF00010D0 );
MMIO_OUT32(MMIO, 0x002D10 , 0xC0000400 );
#endif
MMIO_OUT32(MMIO, 0x002814, 0x00000000 );
#if 0
MMIO_OUT32(MMIO, 0x002818 , 0x00036C20 );
#else
MMIO_OUT32(MMIO, 0x002818 , 0x00036020 );
#endif
MMIO_OUT32(MMIO, 0x00281C , 0x00098081 );
printf("first TRI\n");
clr.f = 5.0;
MMIO_OUT32(MMIO, 0x002820 , clr.i );
clr.f = 595.0;
MMIO_OUT32(MMIO, 0x002824 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002828 , clr.i );
MMIO_OUT32(MMIO, 0x00282C , 0x00FF00 );
#if 0
clr.f = 0.0;
MMIO_OUT32(MMIO, 0x002830 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002834 , clr.i );
#endif
clr.f = 5.0;
MMIO_OUT32(MMIO, 0x002820 , clr.i );
clr.f = 5.0;
MMIO_OUT32(MMIO, 0x002824 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002828 , clr.i );
MMIO_OUT32(MMIO, 0x00282C , 0xFF0000 );
#if 0
clr.f = 0.0;
MMIO_OUT32(MMIO, 0x002830 , clr.i );
clr.f = 0.0;
MMIO_OUT32(MMIO, 0x002834 , clr.i );
#endif
clr.f = 395.0;
printf("0x%x\n",clr.i);
MMIO_OUT32(MMIO, 0x002820 , clr.i );
clr.f = 5.0;
MMIO_OUT32(MMIO, 0x002824 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002828 , clr.i );
MMIO_OUT32(MMIO, 0x00282C , 0xFF );
#if 0
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002830 , clr.i );
clr.f = 0.0;
MMIO_OUT32(MMIO, 0x002834 , clr.i );
#endif
printf("sec TRI\n");
MMIO_OUT32(MMIO, 0x00281C , 0x00093980 );
clr.f = 395.0;
MMIO_OUT32(MMIO, 0x002820 , clr.i );
clr.f = 595.0;
MMIO_OUT32(MMIO, 0x002824 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002828 , clr.i );
MMIO_OUT32(MMIO, 0x00282C , 0x00FF00 );
#if 0
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002830 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002834 , clr.i );
#endif
#if 0
MMIO_OUT32(MMIO, 0x002368 , MMIO_IN32(MMIO,0x002368)&0xfffffffe );
#endif
printf("fin TRI\n");
return 0;
}
static kgi_u8_t virge_chipset_ddc1_get_sda (virge_chipset_io_t * virge_io) {
return (MMIO_IN32(LPB_SERIALPORT) & 0x8 ) >> 3;
}
kgi_error_t virge_chipset_irq_handler(virge_chipset_t *virge, virge_chipset_io_t *virge_io, irq_system_t *system)
{
kgi_u32_t handled = 0;
/* Get interrupt status and clear pending interrupts immediately */
kgi_u32_t sss = MMIO_IN32 (SUBSYSTEM_STATUS);
kgi_u32_t lif = MMIO_IN32 (LPB_INTR_FLAGS);
MMIO_OUT32(SSC_CLEAR_ALL_INTERRUPTS, SUBSYSTEM_CONTROL);
MMIO_OUT32(virge->misc.subsys_ctl, SUBSYSTEM_CONTROL);
CRT_OUT8(virge_io, CRT_IN8(virge_io, 0x11)&~0x30,0x11);
if (virge->misc.subsys_ctl & SSC_VSY_ENB)
CRT_OUT8(virge_io, CRT_IN8(virge_io, 0x11)|0x10,0x11);
/* Now act on pending interrupts. */
KRN_DEBUG(3, "Interrupt: SSS=0x%.8x",sss);
if (sss & SSS_VSY_INT)
{
/* Vertical Sync Interrupt */
handled |= SSS_VSY_INT;
KRN_TRACE(0, virge->interrupt.VSY++);
KRN_DEBUG(1, "VSY interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_S3D_DON)
{
/* 3D Engine done */
handled |= SSS_S3D_DON;
KRN_TRACE(0, virge->interrupt.S3D_DON++);
KRN_DEBUG(1, "S3D_DON interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_FIFO_OVF)
{
/* Command FIFO Overflow */
handled |= SSS_FIFO_OVF;
KRN_TRACE(0, virge->interrupt.FIFO_OVF++);
KRN_DEBUG(1, "FIFO_OVF interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_FIFO_EMP)
{
/* Command FIFO Empty */
handled |= SSS_FIFO_EMP;
KRN_TRACE(0, virge->interrupt.FIFO_EMP++);
KRN_DEBUG(1, "FIFO_EMP interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_HD_DON)
{
/* Host DMA Done */
handled |= SSS_HD_DON;
KRN_TRACE(0, virge->interrupt.HD_DON++);
KRN_DEBUG(1, "HD_DON interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_CD_DON)
{
/* Command DMA Done */
handled |= SSS_CD_DON;
KRN_TRACE(0, virge->interrupt.CD_DON++);
KRN_DEBUG(1, "CD_DON interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_S3DF_FIF)
{
/* S3d FIFO Empty */
handled |= SSS_S3DF_FIF;
KRN_TRACE(0, virge->interrupt.S3DF_FIF++);
KRN_DEBUG(1, "S3DF_FIF interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_LPB_INT)
{
/* LPB Interrupt */
handled |= SSS_LPB_INT;
KRN_TRACE(0, virge->interrupt.LPB_INT++);
KRN_DEBUG(1, "LPB_INT interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (lif & LIF_SPS)
{
/* Serial Port Start */
KRN_TRACE(0, virge->interrupt.SPS++);
KRN_DEBUG(1, "SPS interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & ~handled & 0x000000ff)
{
KRN_TRACE(0, virge->interrupt.not_handled++);
KRN_ERROR("virge: unhandled interrupt flag(s) %.8x (pcidev %.8x)", sss & ~handled, VIRGE_PCIDEV(virge_io));
}
if (!(sss & 0x000000ff))
{
KRN_TRACE(0, virge->interrupt.no_reason++);
KRN_ERROR("virge: interrupt but no reason indicated.");
}
return KGI_EOK;
}
CARD32 xf86PeekMmio32(pointer Base, unsigned long Offset)
{
return MMIO_IN32(Base,Offset);
}
