#include <cpu.h> #include <dm.h> #include <asm/cpu.h> #include <asm/lapic.h> #include <asm/mp.h> #include <asm/msr.h> #include <asm/turbo.h> #ifdef CONFIG_SMP static int enable_smis(struct udevice *cpu, void *unused) { return 0; } static struct mp_flight_record mp_steps[] = { MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), /* Wait for APs to finish initialization before proceeding. */ MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), }; static int detect_num_cpus(void) { int ecx = 0; /* * Use the algorithm described in Intel 64 and IA-32 Architectures * Software Developer's Manual Volume 3 (3A, 3B & 3C): System * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping * of CPUID Extended Topology Leaf. */ while (1) {
#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <reg_script.h> #include <baytrail/msr.h> #include <baytrail/pattrs.h> #include <baytrail/ramstage.h> #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) #include <baytrail/smm.h> static void smm_relocate(void *unused); static void enable_smis(void *unused); static struct mp_flight_record mp_steps[] = { MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), /* Wait for APs to finish initialization before proceeding. */ MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), }; #else /* CONFIG_HAVE_SMI_HANDLER */ static struct mp_flight_record mp_steps[] = { MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), }; #endif /* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ static int adjust_apic_id(int index, int apic_id) { return 2 * index; }