int mt76_mac_start(struct mt76_dev *dev) { int i; for (i = 0; i < 16; i++) mt76_rr(dev, MT_TX_AGG_CNT(i)); for (i = 0; i < 16; i++) mt76_rr(dev, MT_TX_STAT_FIFO); memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats)); mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); wait_for_wpdma(dev); udelay(50); mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_EN); mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter); mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); mt76_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | MT_INT_TX_STAT); return 0; }
int mt76x2_mac_start(struct mt76x02_dev *dev) { int i; for (i = 0; i < 16; i++) mt76_rr(dev, MT_TX_AGG_CNT(i)); for (i = 0; i < 16; i++) mt76_rr(dev, MT_TX_STAT_FIFO); memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats)); mt76x02_mac_start(dev); return 0; }
void mt76x2_mac_work(struct work_struct *work) { struct mt76x2_dev *dev = container_of(work, struct mt76x2_dev, mac_work.work); int i, idx; mt76x2_update_channel(&dev->mt76); for (i = 0, idx = 0; i < 16; i++) { u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); dev->aggr_stats[idx++] += val & 0xffff; dev->aggr_stats[idx++] += val >> 16; } ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mac_work, MT_CALIBRATE_INTERVAL); }