/** * The interrupt handler for the master mode. It does the protocol handling for * the interrupt-driven transfers. * * Completion events and errors are signaled to upper layer for proper handling. * * <pre> * The interrupts that are handled are: * - DATA * This case is handled only for master receive data. * The master has to request for more data (if there is more data to * receive) and read the data from the FIFO . * * - COMP * If the Master is transmitting data and there is more data to be * sent then the data is written to the FIFO. If there is no more data to * be transmitted then a completion event is signalled to the upper layer * by calling the callback handler. * * If the Master is receiving data then the data is read from the FIFO and * the Master has to request for more data (if there is more data to * receive). If all the data has been received then a completion event * is signalled to the upper layer by calling the callback handler. * It is an error if the amount of received data is more than expected. * * - NAK and SLAVE_RDY * This is signalled to the upper layer by calling the callback handler. * * - All Other interrupts * These interrupts are marked as error. This is signalled to the upper * layer by calling the callback handler. * * </pre> * * @param InstancePtr is a pointer to the XIicPs instance. * * @return None. * * @note None. * ****************************************************************************/ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr) { u32 IntrStatusReg; u32 StatusEvent = 0; u32 BaseAddr; int ByteCnt; int IsHold; /* * Assert validates the input arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); BaseAddr = InstancePtr->Config.BaseAddress; /* * Read the Interrupt status register. */ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); /* * Write the status back to clear the interrupts so no events are * missed while processing this interrupt. */ XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); /* * Use the Mask register AND with the Interrupt Status register so * disabled interrupts are not processed. */ IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET)); ByteCnt = InstancePtr->CurrByteCount; IsHold = 0; if (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & XIICPS_CR_HOLD_MASK) { IsHold = 1; } /* * Send */ if ((InstancePtr->IsSend) && (0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) { if (InstancePtr->SendByteCount > 0) { MasterSendData(InstancePtr); } else { StatusEvent |= XIICPS_EVENT_COMPLETE_SEND; } } /* * Receive */ if ((!(InstancePtr->IsSend)) && ((0 != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) || (0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK)))){ while (XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET) & XIICPS_SR_RXDV_MASK) { if ((InstancePtr->RecvByteCount < XIICPS_DATA_INTR_DEPTH) && IsHold && (!(InstancePtr->IsRepeatedStart))) { IsHold = 0; XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK)); } XIicPs_RecvByte(InstancePtr); ByteCnt--; if (InstancePtr->UpdateTxSize && (ByteCnt == XIICPS_FIFO_DEPTH + 1)) break; } if (InstancePtr->UpdateTxSize && (ByteCnt == XIICPS_FIFO_DEPTH + 1)) { /* * wait while fifo is full */ while(XIicPs_ReadReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET) != (ByteCnt - XIICPS_FIFO_DEPTH)); if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) > XIICPS_MAX_TRANSFER_SIZE) { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, XIICPS_MAX_TRANSFER_SIZE); ByteCnt = XIICPS_MAX_TRANSFER_SIZE + XIICPS_FIFO_DEPTH; }else { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH); InstancePtr->UpdateTxSize = 0; ByteCnt = InstancePtr->RecvByteCount; } } InstancePtr->CurrByteCount = ByteCnt; } if ((!(InstancePtr->IsSend)) && (0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) { /* * If all done, tell the application. */ if (InstancePtr->RecvByteCount == 0){ if (!(InstancePtr->IsRepeatedStart)) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK)); } StatusEvent |= XIICPS_EVENT_COMPLETE_RECV; } } /* * Slave ready interrupt, it is only meaningful for master mode. */ if (0 != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) { StatusEvent |= XIICPS_EVENT_SLAVE_RDY; } if (0 != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) { if (!(InstancePtr->IsRepeatedStart)) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK)); } StatusEvent |= XIICPS_EVENT_NACK; } /* * All other interrupts are treated as error. */ if (0 != (IntrStatusReg & (XIICPS_IXR_NACK_MASK | XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK | XIICPS_IXR_RX_OVR_MASK))) { if (!(InstancePtr->IsRepeatedStart)) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK)); } StatusEvent |= XIICPS_EVENT_ERROR; } /* * Signal application if there are any events. */ if (0 != StatusEvent) { InstancePtr->StatusHandler(InstancePtr->CallBackRef, StatusEvent); } }
/** * The interrupt handler for the master mode. It does the protocol handling for * the interrupt-driven transfers. * * Completion events and errors are signaled to upper layer for proper handling. * * <pre> * The interrupts that are handled are: * - DATA * This case is handled only for master receive data. * The master has to request for more data (if there is more data to * receive) and read the data from the FIFO . * * - COMP * If the Master is transmitting data and there is more data to be * sent then the data is written to the FIFO. If there is no more data to * be transmitted then a completion event is signalled to the upper layer * by calling the callback handler. * * If the Master is receiving data then the data is read from the FIFO and * the Master has to request for more data (if there is more data to * receive). If all the data has been received then a completion event * is signalled to the upper layer by calling the callback handler. * It is an error if the amount of received data is more than expected. * * - NAK and SLAVE_RDY * This is signalled to the upper layer by calling the callback handler. * * - All Other interrupts * These interrupts are marked as error. This is signalled to the upper * layer by calling the callback handler. * * </pre> * * @param InstancePtr is a pointer to the XIicPs instance. * * @return None. * * @note None. * ****************************************************************************/ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr) { u32 IntrStatusReg; u32 StatusEvent = 0U; u32 BaseAddr; u16 SlaveAddr; s32 ByteCnt; s32 IsHold; u32 Platform; /* * Assert validates the input arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); BaseAddr = InstancePtr->Config.BaseAddress; Platform = XGetPlatform_Info(); /* * Read the Interrupt status register. */ IntrStatusReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ISR_OFFSET); /* * Write the status back to clear the interrupts so no events are * missed while processing this interrupt. */ XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg); /* * Use the Mask register AND with the Interrupt Status register so * disabled interrupts are not processed. */ IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET)); ByteCnt = InstancePtr->CurrByteCount; IsHold = 0; if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) { IsHold = 1; } /* * Send */ if (((InstancePtr->IsSend) != 0) && ((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) { if (InstancePtr->SendByteCount > 0) { MasterSendData(InstancePtr); } else { StatusEvent |= XIICPS_EVENT_COMPLETE_SEND; } } /* * Receive */ if (((!(InstancePtr->IsSend))!= 0) && ((0 != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) || (0 != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){ while ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_SR_OFFSET) & XIICPS_SR_RXDV_MASK) != 0U) { if (((InstancePtr->RecvByteCount < XIICPS_DATA_INTR_DEPTH)!= 0U) && (IsHold != 0) && ((!InstancePtr->IsRepeatedStart)!= 0) && (InstancePtr->UpdateTxSize == 0)) { IsHold = 0; XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK)); } XIicPs_RecvByte(InstancePtr); ByteCnt--; if (Platform == (u32)XPLAT_ZYNQ) { if ((InstancePtr->UpdateTxSize != 0) && (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) { break; } } } if (Platform == (u32)XPLAT_ZYNQ) { if ((InstancePtr->UpdateTxSize != 0) && (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) { /* wait while fifo is full */ while (XIicPs_ReadReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET) != (u32)(ByteCnt - XIICPS_FIFO_DEPTH)) { } if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) > (s32)XIICPS_MAX_TRANSFER_SIZE) { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, XIICPS_MAX_TRANSFER_SIZE); ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE + XIICPS_FIFO_DEPTH; } else { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH); InstancePtr->UpdateTxSize = 0; ByteCnt = InstancePtr->RecvByteCount; } } } else { if ((InstancePtr->RecvByteCount > 0) && (ByteCnt == 0)) { /* * Clear the interrupt status register before use it to * monitor. */ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET); XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); if ((InstancePtr->RecvByteCount) > (s32)XIICPS_MAX_TRANSFER_SIZE) { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, XIICPS_MAX_TRANSFER_SIZE); ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE; } else { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, InstancePtr->RecvByteCount); InstancePtr->UpdateTxSize = 0; ByteCnt = InstancePtr->RecvByteCount; } XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_ARB_LOST_MASK); } } InstancePtr->CurrByteCount = ByteCnt; } if (((!(InstancePtr->IsSend)) != 0) && (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) { /* * If all done, tell the application. */ if (InstancePtr->RecvByteCount == 0){ if ((!(InstancePtr->IsRepeatedStart)) != 0) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK)); } StatusEvent |= XIICPS_EVENT_COMPLETE_RECV; } } /* * Slave ready interrupt, it is only meaningful for master mode. */ if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) { StatusEvent |= XIICPS_EVENT_SLAVE_RDY; } if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) { if ((!(InstancePtr->IsRepeatedStart)) != 0 ) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK)); } StatusEvent |= XIICPS_EVENT_NACK; } /* * Arbitration lost interrupt */ if (0U != (IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK)) { StatusEvent |= XIICPS_EVENT_ARB_LOST; } /* * All other interrupts are treated as error. */ if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK | XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK | XIICPS_IXR_RX_OVR_MASK))) { if ((!(InstancePtr->IsRepeatedStart)) != 0) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK)); } StatusEvent |= XIICPS_EVENT_ERROR; } /* * Signal application if there are any events. */ if (StatusEvent != 0U) { InstancePtr->StatusHandler(InstancePtr->CallBackRef, StatusEvent); } }