BOOLEAN STATIC MemConstructRemoteNBBlockC32 ( IN OUT MEM_NB_BLOCK *NBPtr, IN DIE_STRUCT *MCTPtr, IN MEM_FEAT_BLOCK_NB *FeatPtr ) { CPU_SPECIFIC_SERVICES *FamilySpecificServices; NBPtr->MCTPtr = MCTPtr; NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; MemNInitNBDataC32 (NBPtr); FeatPtr->InitCPG (NBPtr); NBPtr->FeatPtr = FeatPtr; FeatPtr->InitHwRxEn (NBPtr); MemNSwitchDCTNb (NBPtr, 0); //---------------------------------------------------------------------------- // Get TSC rate of the this AP //---------------------------------------------------------------------------- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); return TRUE; }
BOOLEAN MemConstructNBBlockC32 ( IN OUT MEM_NB_BLOCK *NBPtr, IN OUT MEM_DATA_STRUCT *MemPtr, IN MEM_FEAT_BLOCK_NB *FeatPtr, IN MEM_SHARED_DATA *SharedPtr, IN UINT8 NodeID ) { UINT8 Dct; UINT8 Channel; UINT8 SpdSocketIndex; UINT8 SpdChannelIndex; DIE_STRUCT *MCTPtr; ALLOCATE_HEAP_PARAMS AllocHeapParams; // // Determine if this is the expected NB Type // GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { return FALSE; } NBPtr->MemPtr = MemPtr; NBPtr->RefPtr = MemPtr->ParameterListPtr; NBPtr->SharedPtr = SharedPtr; MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); NBPtr->MCTPtr = MCTPtr; NBPtr->MCTPtr->NodeId = NodeID; NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); // // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs // AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_C32 * ( sizeof (DCT_STRUCT) + ( MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) ) ); AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); AllocHeapParams.Persist = HEAP_LOCAL_CACHE; if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); SetMemError (AGESA_FATAL, MCTPtr); ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs return FALSE; } MCTPtr->DctCount = MAX_DCTS_PER_NODE_C32; MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_C32 * sizeof (DCT_STRUCT); for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { MCTPtr->DctData[Dct].Dct = Dct; MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_C32; MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; MCTPtr->DctData[Dct].ChData[0].Dct = Dct; AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_C32 * sizeof (CH_DEF_STRUCT); } NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; // // Initialize Socket List // for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]); MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings); MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; } MemNInitNBDataC32 (NBPtr); FeatPtr->InitCPG (NBPtr); NBPtr->FeatPtr = FeatPtr; FeatPtr->InitHwRxEn (NBPtr); // // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the // dimm types(QR or not) are known. This is done in the Technology block constructor. // // Calculate the SpdSocketIndex separately from the SpdChannelIndex. // This will facilitate modifications due to some processors that might // map the DCT-CHANNEL differently. // SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); // // Traverse the Dct/Channel structures // for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_C32; Channel++) { // // Calculate the number of Dimms on this channel using the // die/dct/channel to Socket/channel conversion. // SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelC32 (NBPtr, Dct, Channel), &MemPtr->StdHeader); NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); } } MemNSwitchDCTNb (NBPtr, 0); return TRUE; }