/**These functions are NOT opcodes!**/ SPEED_UP unsigned int push(unsigned short val){ unsigned short *ptr; gregs16[SP]--;gregs16[SP]--; //maybe we can get an optimization out of it.. //ptr=core+gregs16[SP]+sregs[SS]; return MemWrite16(SS,gregs16[SP],&val); //*ptr=val; }
void mov_mem16_ax(){ unsigned short tmp; ip++; MemRead16(CS,ip,&tmp); ip++; MemWrite16(CurrentSegment,tmp,&gregs16[AX]); }
static UINT32 am3DirectAddressDeferred(void) { switch (modDim) { case 0: MemWrite8(MemRead32(OpRead32(modAdd+1)), modWriteValB); break; case 1: MemWrite16(MemRead32(OpRead32(modAdd+1)), modWriteValH); break; case 2: MemWrite32(MemRead32(OpRead32(modAdd+1)), modWriteValW); break; } return 5; }
static UINT32 am3PCDoubleDisplacement32(void) { switch (modDim) { case 0: MemWrite8(MemRead32(PC + OpRead32(modAdd+1)) + OpRead32(modAdd+5), modWriteValB); break; case 1: MemWrite16(MemRead32(PC + OpRead32(modAdd+1)) + OpRead32(modAdd+5), modWriteValH); break; case 2: MemWrite32(MemRead32(PC + OpRead32(modAdd+1)) + OpRead32(modAdd+5), modWriteValW); break; } return 9; }
static UINT32 am3PCDoubleDisplacement16(void) { switch (modDim) { case 0: MemWrite8(MemRead32(PC + (INT16)OpRead16(modAdd+1)) + (INT16)OpRead16(modAdd+3), modWriteValB); break; case 1: MemWrite16(MemRead32(PC + (INT16)OpRead16(modAdd+1)) + (INT16)OpRead16(modAdd+3), modWriteValH); break; case 2: MemWrite32(MemRead32(PC + (INT16)OpRead16(modAdd+1)) + (INT16)OpRead16(modAdd+3), modWriteValW); break; } return 5; }
static UINT32 am3DoubleDisplacement8(void) { switch (modDim) { case 0: MemWrite8(MemRead32(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1)) + (INT8)OpRead8(modAdd+2), modWriteValB); break; case 1: MemWrite16(MemRead32(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1)) + (INT8)OpRead8(modAdd+2), modWriteValH); break; case 2: MemWrite32(MemRead32(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1)) + (INT8)OpRead8(modAdd+2), modWriteValW); break; } return 3; }
static UINT32 am3PCDisplacementIndirectIndexed32(void) { switch (modDim) { case 0: MemWrite8(MemRead32(PC + OpRead32(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValB); break; case 1: MemWrite16(MemRead32(PC + OpRead32(modAdd+2)) + v60.reg[modVal&0x1F] * 2, modWriteValH); break; case 2: MemWrite32(MemRead32(PC + OpRead32(modAdd+2)) + v60.reg[modVal&0x1F] * 4, modWriteValW); break; } return 6; }
static UINT32 am3RegisterIndirectIndexed(void) { switch (modDim) { case 0: MemWrite8(v60.reg[modVal2&0x1F] + v60.reg[modVal&0x1F], modWriteValB); break; case 1: MemWrite16(v60.reg[modVal2&0x1F] + v60.reg[modVal&0x1F] * 2, modWriteValH); break; case 2: MemWrite32(v60.reg[modVal2&0x1F] + v60.reg[modVal&0x1F] * 4, modWriteValW); break; } return 2; }
static UINT32 am3DisplacementIndirect32(void) { switch (modDim) { case 0: MemWrite8(MemRead32(v60.reg[modVal&0x1F] + OpRead32(modAdd+1)), modWriteValB); break; case 1: MemWrite16(MemRead32(v60.reg[modVal&0x1F] + OpRead32(modAdd+1)), modWriteValH); break; case 2: MemWrite32(MemRead32(v60.reg[modVal&0x1F] + OpRead32(modAdd+1)), modWriteValW); break; } return 5; }
static UINT32 am3PCDisplacementIndexed16(void) { switch (modDim) { case 0: MemWrite8(PC + (INT16)OpRead16(modAdd+2) + v60.reg[modVal&0x1F], modWriteValB); break; case 1: MemWrite16(PC + (INT16)OpRead16(modAdd+2) + v60.reg[modVal&0x1F] * 2, modWriteValH); break; case 2: MemWrite32(PC + (INT16)OpRead16(modAdd+2) + v60.reg[modVal&0x1F] * 4, modWriteValW); break; } return 4; }
static UINT32 am3DisplacementIndexed8(void) { switch (modDim) { case 0: MemWrite8(v60.reg[modVal2&0x1F] + (INT8)OpRead8(modAdd+2) + v60.reg[modVal&0x1F], modWriteValB); break; case 1: MemWrite16(v60.reg[modVal2&0x1F] + (INT8)OpRead8(modAdd+2) + v60.reg[modVal&0x1F] * 2, modWriteValH); break; case 2: MemWrite32(v60.reg[modVal2&0x1F] + (INT8)OpRead8(modAdd+2) + v60.reg[modVal&0x1F] * 4, modWriteValW); break; } return 3; }
static UINT32 am3Displacement16(void) { switch (modDim) { case 0: MemWrite8(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1), modWriteValB); break; case 1: MemWrite16(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1), modWriteValH); break; case 2: MemWrite32(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1), modWriteValW); break; } return 3; }
static UINT32 am3DirectAddressDeferredIndexed(void) { switch (modDim) { case 0: MemWrite8(MemRead32(OpRead32(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValB); break; case 1: MemWrite16(MemRead32(OpRead32(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValH); break; case 2: MemWrite32(MemRead32(OpRead32(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValW); break; } return 6; }
static UINT32 am3PCDisplacementIndirect8(void) { switch (modDim) { case 0: MemWrite8(MemRead32(PC + (INT8)OpRead8(modAdd+1)), modWriteValB); break; case 1: MemWrite16(MemRead32(PC + (INT8)OpRead8(modAdd+1)), modWriteValH); break; case 2: MemWrite32(MemRead32(PC + (INT8)OpRead8(modAdd+1)), modWriteValW); break; } return 2; }
static UINT32 am3Autoincrement(void) { switch (modDim) { case 0: MemWrite8(v60.reg[modVal&0x1F], modWriteValB); v60.reg[modVal&0x1F] += 1; break; case 1: MemWrite16(v60.reg[modVal&0x1F], modWriteValH); v60.reg[modVal&0x1F] += 2; break; case 2: MemWrite32(v60.reg[modVal&0x1F], modWriteValW); v60.reg[modVal&0x1F] += 4; break; } return 1; }
static UINT32 am3Autodecrement(void) { switch (modDim) { case 0: v60.reg[modVal&0x1F] -= 1; MemWrite8(v60.reg[modVal&0x1F], modWriteValB); break; case 1: v60.reg[modVal&0x1F] -= 2; MemWrite16(v60.reg[modVal&0x1F], modWriteValH); break; case 2: v60.reg[modVal&0x1F] -= 4; MemWrite32(v60.reg[modVal&0x1F], modWriteValW); break; } return 1; }
UINT32 opDECH(void) /* TRUSTED */ { UINT16 apph; modAdd=PC+1; modDim=1; amLength1=ReadAMAddress(); if (amFlag) apph=(UINT16)v60.reg[amOut]; else apph=MemRead16(amOut); SUBW(apph, 1); if (amFlag) SETREG16(v60.reg[amOut], apph); else MemWrite16(amOut, apph); return amLength1+1; }