void FASTCALL WriteMem_A0_006(u32 addr,u32 data,u32 size)
{
switch(settings.mode)
{
case 0:
return;
case 1:
ModemWriteMem_A0_006(addr,data,size);
return;
case 2:
LanWriteMem_A0_006(addr,data,size);
return;
default:
//printf("Write to modem area on mode %d, addr[%d] 0x%08X=0x%08X\n",settings.mode,size,addr,data);
return;
}
}
void DYNACALL WriteMem_area0(u32 addr,T data)
{
addr &= 0x01FFFFFF;//to get rid of non needed bits
const u32 base=(addr>>16);
//map 0x0000 to 0x001F
#if DC_PLATFORM != DC_PLATFORM_ATOMISWAVE
if ((base <=0x001F) /*&& (addr<=0x001FFFFF)*/)// :MPX System/Boot ROM
#else
if (base <= 0x0001) // Only 128k BIOS on AtomisWave
#endif
{
WriteBios(addr,data,sz);
}
//map 0x0020 to 0x0021
else if ((base >=0x0020) && (base <=0x0021) /*&& (addr>= 0x00200000) && (addr<= 0x0021FFFF)*/) // Flash Memory
{
WriteFlash(addr,data,sz);
}
//map 0x0040 to 0x005F -> actually, I'll only map 0x005F to 0x005F, b/c the rest of it is unspammed (left to default handler)
//map 0x005F to 0x005F
else if ( likely(base==0x005F) )
{
if (/*&& (addr>= 0x00400000) */ (addr<= 0x005F67FF)) // Unassigned
{
EMUERROR4("Write to area0_32 not implemented [Unassigned], addr=%x,data=%x,size=%d",addr,data,sz);
}
else if ((addr>= 0x005F7000) && (addr<= 0x005F70FF)) // GD-ROM
{
#if DC_PLATFORM == DC_PLATFORM_NAOMI || DC_PLATFORM == DC_PLATFORM_ATOMISWAVE
WriteMem_naomi(addr,data,sz);
#else
WriteMem_gdrom(addr,data,sz);
#endif
}
else if ( likely((addr>= 0x005F6800) && (addr<=0x005F7CFF)) ) // /*:PVR i/f Control Reg.*/ -> ALL SB registers
{
sb_WriteMem(addr,data,sz);
}
else if ( likely((addr>= 0x005F8000) && (addr<=0x005F9FFF)) ) // TA / PVR Core Reg.
{
verify(sz==4);
pvr_WriteReg(addr,data);
}
}
//map 0x0060 to 0x0060
else if ((base ==0x0060) /*&& (addr>= 0x00600000)*/ && (addr<= 0x006007FF)) // MODEM
{
#if DC_PLATFORM == DC_PLATFORM_NAOMI || DC_PLATFORM == DC_PLATFORM_ATOMISWAVE
libExtDevice_WriteMem_A0_006(addr, data, sz);
#elif defined(ENABLE_MODEM)
ModemWriteMem_A0_006(addr, data, sz);
#endif
}
//map 0x0060 to 0x006F
else if ((base >=0x0060) && (base <=0x006F) && (addr>= 0x00600800) && (addr<= 0x006FFFFF)) // G2 (Reserved)
{
EMUERROR4("Write to area0_32 not implemented [G2 (Reserved)], addr=%x,data=%x,size=%d",addr,data,sz);
}
//map 0x0070 to 0x0070
else if ((base >=0x0070) && (base <=0x0070) /*&& (addr>= 0x00700000)*/ && (addr<=0x00707FFF)) // AICA- Sound Cntr. Reg.
{
WriteMem_aica_reg(addr,data,sz);
return;
}
//map 0x0071 to 0x0071
else if ((base >=0x0071) && (base <=0x0071) /*&& (addr>= 0x00710000)*/ && (addr<= 0x0071000B)) // AICA- RTC Cntr. Reg.
{
WriteMem_aica_rtc(addr,data,sz);
return;
}
//map 0x0080 to 0x00FF
else if ((base >=0x0080) && (base <=0x00FF) /*&& (addr>= 0x00800000) && (addr<=0x00FFFFFF)*/) // AICA- Wave Memory
{
WriteMemArrRet(aica_ram.data,addr&ARAM_MASK,data,sz);
return;
}
//map 0x0100 to 0x01FF
else if ((base >=0x0100) && (base <=0x01FF) /*&& (addr>= 0x01000000) && (addr<= 0x01FFFFFF)*/) // Ext. Device
{
libExtDevice_WriteMem_A0_010(addr,data,sz);
}
return;
}
