static void nand_read_page(u32 page_addr, u32 dest_addr)
{
int i;
u8 *tmp;
u8 col_addr_num;
u8 page_addr_num;
if(CONFIG_NAND_PAGE_SIZE<=0x200) {
col_addr_num=1;
if(CONFIG_NAND_FLASH_SIZE<32) {
page_addr_num=2;
} else
page_addr_num=3;
} else {
col_addr_num=2;
if(CONFIG_NAND_FLASH_SIZE<128) {
page_addr_num=2;
} else {
page_addr_num=3;
}
}
NAND_CE_SET;
NAND_SETCLE;
NAND_WRITE(WRITE_CMD,0);
NAND_CLRCLE;
NAND_SETALE;
for(i=0; i<col_addr_num; i++) {
NAND_WRITE(WRITE_ADDR,0);
}
for(i=0; i<page_addr_num; i++) {
NAND_WRITE(WRITE_ADDR,(u8)((page_addr>>(i*8)) & 0xff ));
}
NAND_CLRALE;
NAND_SETCLE;
if(CONFIG_NAND_PAGE_SIZE>0x200) {
NAND_WRITE(WRITE_CMD,0x30);
}
NAND_CLRCLE;
while(!NAND_READY) {}
/* Read page */
tmp = (u8*)dest_addr;
for (i = 0; i < CONFIG_NAND_PAGE_SIZE; i++)
{
NAND_READ(READ_DATA, *tmp++);
}
NAND_CE_CLEAR;
while(!NAND_READY) {}
}
/*!
\fn void ifx_nand_chip_init(void)
\ingroup IFX_NAND_DRV
\brief platform specific initialization routine
\param none
\return none
*/
static void ifx_nand_chip_init(void)
{
u32 reg;
/*P1.7 FL_CS1 used as output*/
ifx_gpio_pin_reserve(IFX_NAND_CS1, IFX_GPIO_MODULE_NAND);
ifx_gpio_dir_out_set(IFX_NAND_CS1, IFX_GPIO_MODULE_NAND);
ifx_gpio_altsel0_set(IFX_NAND_CS1, IFX_GPIO_MODULE_NAND);
ifx_gpio_altsel1_clear(IFX_NAND_CS1, IFX_GPIO_MODULE_NAND);
ifx_gpio_open_drain_set(IFX_NAND_CS1, IFX_GPIO_MODULE_NAND);
/*P1.8 FL_A23 NAND_CLE used as output*/
ifx_gpio_pin_reserve(IFX_NAND_CLE, IFX_GPIO_MODULE_NAND);
ifx_gpio_dir_out_set(IFX_NAND_CLE, IFX_GPIO_MODULE_NAND);
ifx_gpio_altsel0_set(IFX_NAND_CLE, IFX_GPIO_MODULE_NAND);
ifx_gpio_altsel1_clear(IFX_NAND_CLE, IFX_GPIO_MODULE_NAND);
ifx_gpio_open_drain_set(IFX_NAND_CLE, IFX_GPIO_MODULE_NAND);
/*P0.13 FL_A24 used as output, set GPIO 13 to NAND_ALE*/
ifx_gpio_pin_reserve(IFX_NAND_ALE, IFX_GPIO_MODULE_NAND);
ifx_gpio_dir_out_set(IFX_NAND_ALE, IFX_GPIO_MODULE_NAND);
ifx_gpio_altsel0_set(IFX_NAND_ALE, IFX_GPIO_MODULE_NAND);
ifx_gpio_altsel1_clear(IFX_NAND_ALE, IFX_GPIO_MODULE_NAND);
ifx_gpio_open_drain_set(IFX_NAND_ALE, IFX_GPIO_MODULE_NAND);
#if defined(CONFIG_VR9) | defined(CONFIG_AR9)
/*P3.0 set as NAND Read Busy*/
ifx_gpio_pin_reserve(IFX_NAND_RDY, IFX_GPIO_MODULE_NAND);
ifx_gpio_dir_in_set(IFX_NAND_RDY, IFX_GPIO_MODULE_NAND);
ifx_gpio_altsel0_set(IFX_NAND_RDY, IFX_GPIO_MODULE_NAND);
ifx_gpio_altsel1_clear(IFX_NAND_RDY, IFX_GPIO_MODULE_NAND);
/*P3.1 set as NAND Read*/
ifx_gpio_pin_reserve(IFX_NAND_RD, IFX_GPIO_MODULE_NAND);
ifx_gpio_dir_out_set(IFX_NAND_RD, IFX_GPIO_MODULE_NAND);
ifx_gpio_altsel0_set(IFX_NAND_RD, IFX_GPIO_MODULE_NAND);
ifx_gpio_altsel1_clear(IFX_NAND_RD, IFX_GPIO_MODULE_NAND);
ifx_gpio_open_drain_set(IFX_NAND_RD, IFX_GPIO_MODULE_NAND);
#endif
reg = (NAND_BASE_ADDRESS & 0x1fffff00)| IFX_EBU_ADDSEL1_MASK(3)| IFX_EBU_ADDSEL1_REGEN;
IFX_REG_W32(reg,IFX_EBU_ADDSEL1);
/* byte swap;minimum delay*/
reg = IFX_EBU_BUSCON1_SETUP |
SM(IFX_EBU_BUSCON1_ALEC3,IFX_EBU_BUSCON1_ALEC) |
SM(IFX_EBU_BUSCON1_BCGEN_RES,IFX_EBU_BUSCON1_BCGEN) |
SM(IFX_EBU_BUSCON1_WAITWRC2,IFX_EBU_BUSCON1_WAITWRC) |
SM(IFX_EBU_BUSCON1_WAITRDC2,IFX_EBU_BUSCON1_WAITRDC) |
SM(IFX_EBU_BUSCON1_HOLDC1,IFX_EBU_BUSCON1_HOLDC) |
SM(IFX_EBU_BUSCON1_RECOVC1,IFX_EBU_BUSCON1_RECOVC) |
SM(IFX_EBU_BUSCON1_CMULT4,IFX_EBU_BUSCON1_CMULT);
IFX_REG_W32(reg, IFX_EBU_BUSCON1);
reg = SM(IFX_EBU_NAND_CON_NANDM_ENABLE, IFX_EBU_NAND_CON_NANDM) |
SM(IFX_EBU_NAND_CON_CSMUX_E_ENABLE,IFX_EBU_NAND_CON_CSMUX_E) |
SM(IFX_EBU_NAND_CON_CS_P_LOW,IFX_EBU_NAND_CON_CS_P) |
SM(IFX_EBU_NAND_CON_SE_P_LOW,IFX_EBU_NAND_CON_SE_P) |
SM(IFX_EBU_NAND_CON_WP_P_LOW,IFX_EBU_NAND_CON_WP_P) |
SM(IFX_EBU_NAND_CON_PRE_P_LOW,IFX_EBU_NAND_CON_PRE_P) |
SM(IFX_EBU_NAND_CON_IN_CS1,IFX_EBU_NAND_CON_IN_CS) |
SM(IFX_EBU_NAND_CON_OUT_CS1,IFX_EBU_NAND_CON_OUT_CS);
IFX_REG_W32(reg,IFX_EBU_NAND_CON);
asm("sync");
/* Set bus signals to inactive */
NAND_WRITE(NAND_WRITE_CMD, NAND_WRITE_CMD_RESET); // Reset nand chip
}
