static void set_htic_bit(u8 i, u32 val, u8 bit) { u32 dword; dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL); dword &= ~(1<<bit); dword |= ((val & 1) <<bit); pci_write_config32(NODE_PCI(i, 0), HT_INIT_CONTROL, dword); }
static u32 get_htic_bit(u8 i, u8 bit) { u32 dword; dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL); dword &= (1<<bit); return dword; }
static u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; if (is_fam15h()) { /* Family 15h moved CmpCap to F5x84 [7:0] */ dword = pci_read_config32(NODE_PCI(nodeid, 5), 0x84); dword &= 0xff; } else { dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8); dword >>= 12; /* Bit 15 is CmpCap[2] since Revision D. */ if ((cpuid_ecx(0x80000008) & 0xff) > 3) dword = ((dword & 8) >> 1) | (dword & 3); else dword &= 3; }
static u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8); dword >>= 12; /* Bit 15 is CmpCap[2] since Revision D. */ if ((cpuid_ecx(0x80000008) & 0xff) > 3) dword = ((dword & 8) >> 1) | (dword & 3); else
static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; u32 tempreg; device_t dev; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit for(i=0; i<nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for(i=0; i<nodes; i++){ dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); } }
static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr) { int i; int j; int index = 0; struct mem_controller *ctrl; for (i=0;i<controllers; i++) { ctrl = &ctrl_a[i]; ctrl->node_id = i; ctrl->f0 = NODE_PCI(i, 0); ctrl->f1 = NODE_PCI(i, 1); ctrl->f2 = NODE_PCI(i, 2); ctrl->f3 = NODE_PCI(i, 3); ctrl->f4 = NODE_PCI(i, 4); ctrl->f5 = NODE_PCI(i, 5); if (spd_addr == (void *)0) continue; ctrl->spd_switch_addr = spd_addr[index++]; for (j=0; j < 8; j++) { ctrl->spd_addr[j] = spd_addr[index++]; } } }
static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; device_t dev; /* io range allocation */ for(i=0; i<nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); } }