/*
******************************************************************************
** VOID BSP_WakeupCpuIntISR(VOID)
**
** Description : Wakeup cpu INT handler
** Arguments :
** Returns : 无
** Author :
** Date :
**
******************************************************************************
*/
VOID BSP_WakeupCpuIntISR(VOID)
{
NST_TskMsg* msg;
//DBGPRINT_PS(DEBUG_TRACE, "MLME_AUTO_WAKEUP_ID\n");
//Set Mask
NST_WR_PWM_REG(ADDR_WAKEUP_CPU_MASK, 0x00000003);
// 关WAKE UP中断
NVIC_DisableIRQ(WAKEUP_CPU_IRQn);
/* 清M3 的中断*/
NVIC_ClearIRQChannelPendingBit(WAKEUP_CPU_IRQn);
//发消息给syscore
msg = NST_AllocTskMsg();
if(msg)
{
msg->msgId = MLME_AUTO_WAKEUP_ID;
// NST_ZERO_MEM(msg->msgBody, sizeof(msg->msgBody));
NST_SendMsg(gpMacMngTskMsgQ, msg);
}
// 开中断
NVIC_EnableIRQ(WAKEUP_CPU_IRQn);
}
VOID BSP_QSpiInit(UINT16 SpiClkDiv)
{
// SPIpins can't used as GPIO
NST_WR_PWM_REG(ADDR_GPIO_PIN_MUX_CTRL, NST_RD_PWM_REG(ADDR_GPIO_PIN_MUX_CTRL) & (~ENA_QSPIM_GPIO));
NST_QSPI->SSIENR= 0x00;
NST_QSPI->IMR= 0x00;
//NST_QSPI->DMACR= 0x00;
//NST_QSPI->DMATDLR= 0x00;
NST_QSPI->BAUDR= SpiClkDiv;
NST_QSPI->CTRLR0= (QSPI_TMOD_TR << QSPI_TMOD_OFFSET) | (QSPI_FRF_QSPI << QSPI_FRF_OFFSET) |(QSPI_FRM_SIZE - 1) |( QSPI_MODE_3 << 6);
NST_QSPI->CTRLR1= 0x00;
//NST_QSPI->SER= 0x01;
NST_QSPI->SSIENR= 0x01;
}
/*
******************************************************************************
** VOID BSP_ClkInit ()
**
** Description : BSP CLK mode
** Arguments :
** Returns : 无
** Author :
** Date :
**
******************************************************************************
*/
VOID BSP_ClkInit (VOID)
{
// clk init
/*CHIP MODE
31:4 | 5 | 4:3 | 2 | 1:0
Rsv | CPU Sel ena | CPU Sel | Bandwith Ena | Bandwith
CLK_CTRL
31:7 | 4 | 3 | 2 | 1:0
Rsv | APB2_GATE_E | APB1_GATE_E | WLAN_GATE_E | APB_SEL
*/
if(CpuClkFreq == CPU_CLK_FREQ_160M)
{
NST_WR_PWM_REG(ADDR_CHIP_MODE, CHIP_BW_MODE_20M|CHIP_BW_ENA|(CPU_CLK_MODE_160M<<CPU_CLK_SEL)|CPU_SEL_ENA|CHIP_SMID_RST_DONE);
NST_WR_PWM_REG(ADDR_CLK_CTRL, APB_CLK_MODE_40M|WLAN_GATE_ENA|APB1_GATE_ENA|APB2_GATE_ENA);
ApbClkFreq = APB_CLK_FREQ_40M;
}
else if(CpuClkFreq == CPU_CLK_FREQ_120M)
{
NST_WR_PWM_REG(ADDR_CHIP_MODE, CHIP_BW_MODE_20M|CHIP_BW_ENA|(CPU_CLK_MODE_120M<<CPU_CLK_SEL)|CPU_SEL_ENA|CHIP_SMID_RST_DONE);
NST_WR_PWM_REG(ADDR_CLK_CTRL, APB_CLK_MODE_40M|WLAN_GATE_ENA|APB1_GATE_ENA|APB2_GATE_ENA);
ApbClkFreq = APB_CLK_FREQ_40M;
}
else if(CpuClkFreq == CPU_CLK_FREQ_80M)
{
NST_WR_PWM_REG(ADDR_CHIP_MODE, CHIP_BW_MODE_20M|CHIP_BW_ENA|(CPU_CLK_MODE_80M<<CPU_CLK_SEL)|CPU_SEL_ENA|CHIP_SMID_RST_DONE);
NST_WR_PWM_REG(ADDR_CLK_CTRL, APB_CLK_MODE_20M|WLAN_GATE_ENA|APB1_GATE_ENA|APB2_GATE_ENA);
ApbClkFreq = APB_CLK_FREQ_20M;
}
else if(CpuClkFreq == CPU_CLK_FREQ_40M)
{
NST_WR_PWM_REG(ADDR_CHIP_MODE, CHIP_BW_MODE_20M|CHIP_BW_ENA|(CPU_CLK_MODE_40M<<CPU_CLK_SEL)|CPU_SEL_ENA|CHIP_SMID_RST_DONE);
NST_WR_PWM_REG(ADDR_CLK_CTRL, APB_CLK_MODE_10M|WLAN_GATE_ENA|APB1_GATE_ENA|APB2_GATE_ENA);
ApbClkFreq = APB_CLK_FREQ_10M;
}
}
void GPIO_Init(GPIO_InitTypeDef* GPIO_InitStruct)
{
int pin_reg = 0,mode_reg;
/* Check the parameters */
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
/* set ADDR_GPIO_PIN_MUX_CTRL Register*/
pin_reg = NST_RD_PWM_REG(ADDR_GPIO_PIN_MUX_CTRL);
pin_reg |= GPIO_InitStruct->GPIO_Pin;
/* set SWPORTA_DDR Register*/
mode_reg = NST_RD_GPIO_REG(SWPORTA_DDR);
if(GPIO_InitStruct->GPIO_Mode){
mode_reg |= GPIO_InitStruct->GPIO_Pin;
} else {
mode_reg &= ~GPIO_InitStruct->GPIO_Pin;
}
NST_WR_PWM_REG(ADDR_GPIO_PIN_MUX_CTRL, pin_reg);
NST_WR_GPIO_REG(SWPORTA_DDR, mode_reg);
}
