void USBHALHost::init() { NVIC_DisableIRQ(USB_IRQn); //Cut power LPC_SC->PCONP &= ~(1UL<<31); wait_ms(100); // turn on power for USB LPC_SC->PCONP |= (1UL<<31); // Enable USB host clock, port selection and AHB clock LPC_USB->USBClkCtrl |= CLOCK_MASK; // Wait for clocks to become available while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK); // it seems the bits[0:1] mean the following // 0: U1=device, U2=host // 1: U1=host, U2=host // 2: reserved // 3: U1=host, U2=device // NB: this register is only available if OTG clock (aka "port select") is enabled!! // since we don't care about port 2, set just bit 0 to 1 (U1=host) LPC_USB->OTGStCtrl |= 1; // now that we've configured the ports, we can turn off the portsel clock LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN; // configure USB D+/D- pins // P0[29] = USB_D+, 01 // P0[30] = USB_D-, 01 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28)); LPC_PINCON->PINSEL1 |= ((1<<26) | (1<<28)); LPC_USB->HcControl = 0; // HARDWARE RESET LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero LPC_USB->HcBulkHeadED = 0; // Initialize Bulk list head to Zero // Wait 100 ms before apply reset wait_ms(100); // software reset LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR; // Write Fm Interval and Largest Data Packet Counter LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL; LPC_USB->HcPeriodicStart = FI * 90 / 100; // Put HC in operational state LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER; // Set Global Power LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC; LPC_USB->HcHCCA = (uint32_t)(usb_hcca); // Clear Interrrupt Status LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus; LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC; // Enable the USB Interrupt NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr)); LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC; LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC; NVIC_EnableIRQ(USB_IRQn); // Check for any connected devices if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) { //Device connected wait_ms(150); USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1); deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA); } }
void timer_irq_disable(tim_t dev) { NVIC_DisableIRQ(timer_config[dev].irq); }
void gpio_irq_disable(gpio_irq_t *obj) { NVIC_DisableIRQ(EINT3_IRQn); }
void eth_arch_disable_interrupts(void) { NVIC_DisableIRQ(ENET_IRQn); }
int main() { unsigned int stacks[TASK_LIMIT][STACK_SIZE]; //struct task_control_block tasks[TASK_LIMIT]; struct pipe_ringbuffer pipes[PIPE_LIMIT]; struct task_control_block *ready_list[PRIORITY_LIMIT + 1]; /* [0 ... 39] */ struct task_control_block *wait_list = NULL; //size_t task_count = 0; size_t current_task = 0; size_t i; struct task_control_block *task; int timeup; unsigned int tick_count = 0; SysTick_Config(configCPU_CLOCK_HZ / configTICK_RATE_HZ); init_rs232(); __enable_irq(); tasks[task_count].stack = (void*)init_task(stacks[task_count], &first); tasks[task_count].pid = 0; tasks[task_count].priority = PRIORITY_DEFAULT; task_count++; /* Initialize all pipes */ for (i = 0; i < PIPE_LIMIT; i++) pipes[i].start = pipes[i].end = 0; /* Initialize fifos */ for (i = 0; i <= PATHSERVER_FD; i++) _mknod(&pipes[i], S_IFIFO); /* Initialize ready lists */ for (i = 0; i <= PRIORITY_LIMIT; i++) ready_list[i] = NULL; while (1) { tasks[current_task].stack = activate(tasks[current_task].stack); tasks[current_task].status = TASK_READY; timeup = 0; switch (tasks[current_task].stack->r8) { case 0x1: /* fork */ if (task_count == TASK_LIMIT) { /* Cannot create a new task, return error */ tasks[current_task].stack->r0 = -1; } else { /* Compute how much of the stack is used */ size_t used = stacks[current_task] + STACK_SIZE - (unsigned int*)tasks[current_task].stack; /* New stack is END - used */ tasks[task_count].stack = (void*)(stacks[task_count] + STACK_SIZE - used); /* Copy only the used part of the stack */ memcpy(tasks[task_count].stack, tasks[current_task].stack, used * sizeof(unsigned int)); /* Set PID */ tasks[task_count].pid = task_count; /* Set priority, inherited from forked task */ tasks[task_count].priority = tasks[current_task].priority; /* Set return values in each process */ tasks[current_task].stack->r0 = task_count; tasks[task_count].stack->r0 = 0; tasks[task_count].prev = NULL; tasks[task_count].next = NULL; task_push(&ready_list[tasks[task_count].priority], &tasks[task_count]); /* There is now one more task */ task_count++; } break; case 0x2: /* getpid */ tasks[current_task].stack->r0 = current_task; break; case 0x3: /* write */ _write(&tasks[current_task], tasks, task_count, pipes); break; case 0x4: /* read */ _read(&tasks[current_task], tasks, task_count, pipes); break; case 0x5: /* interrupt_wait */ /* Enable interrupt */ NVIC_EnableIRQ(tasks[current_task].stack->r0); /* Block task waiting for interrupt to happen */ tasks[current_task].status = TASK_WAIT_INTR; break; case 0x6: /* getpriority */ { int who = tasks[current_task].stack->r0; if (who > 0 && who < (int)task_count) tasks[current_task].stack->r0 = tasks[who].priority; else if (who == 0) tasks[current_task].stack->r0 = tasks[current_task].priority; else tasks[current_task].stack->r0 = -1; } break; case 0x7: /* setpriority */ { int who = tasks[current_task].stack->r0; int value = tasks[current_task].stack->r1; value = (value < 0) ? 0 : ((value > PRIORITY_LIMIT) ? PRIORITY_LIMIT : value); if (who > 0 && who < (int)task_count) tasks[who].priority = value; else if (who == 0) tasks[current_task].priority = value; else { tasks[current_task].stack->r0 = -1; break; } tasks[current_task].stack->r0 = 0; } break; case 0x8: /* mknod */ if (tasks[current_task].stack->r0 < PIPE_LIMIT) tasks[current_task].stack->r0 = _mknod(&pipes[tasks[current_task].stack->r0], tasks[current_task].stack->r2); else tasks[current_task].stack->r0 = -1; break; case 0x9: /* sleep */ if (tasks[current_task].stack->r0 != 0) { tasks[current_task].stack->r0 += tick_count; tasks[current_task].status = TASK_WAIT_TIME; } break; default: /* Catch all interrupts */ if ((int)tasks[current_task].stack->r8 < 0) { unsigned int intr = -tasks[current_task].stack->r8 - 16; if (intr == SysTick_IRQn) { /* Never disable timer. We need it for pre-emption */ timeup = 1; tick_count++; } else { /* Disable interrupt, interrupt_wait re-enables */ NVIC_DisableIRQ(intr); } /* Unblock any waiting tasks */ for (i = 0; i < task_count; i++) if ((tasks[i].status == TASK_WAIT_INTR && tasks[i].stack->r0 == intr) || (tasks[i].status == TASK_WAIT_TIME && tasks[i].stack->r0 == tick_count)) tasks[i].status = TASK_READY; } } /* Put waken tasks in ready list */ for (task = wait_list; task != NULL;) { struct task_control_block *next = task->next; if (task->status == TASK_READY) task_push(&ready_list[task->priority], task); task = next; } /* Select next TASK_READY task */ for (i = 0; i < (size_t)tasks[current_task].priority && ready_list[i] == NULL; i++); if (tasks[current_task].status == TASK_READY) { if (!timeup && i == (size_t)tasks[current_task].priority) /* Current task has highest priority and remains execution time */ continue; else task_push(&ready_list[tasks[current_task].priority], &tasks[current_task]); } else { task_push(&wait_list, &tasks[current_task]); } while (ready_list[i] == NULL) i++; current_task = task_pop(&ready_list[i])->pid; } return 0; }
/***************************************************************************** Função que recebe o touch pressionado do capacitivo 4x4 *****************************************************************************/ void cmd_rcv_touch(char *par) { char i,touch,str_IdIr[4],str_aux[50],flag_send_ir = __TRUE; memset(str_IdIr,0,sizeof(str_IdIr)); memset(str_aux,0,sizeof(str_aux)); str_IdIr[0] = par[1]; str_IdIr[1] = par[2]; touch = atoi(str_IdIr); if(!(touchEnaDis & (1<<touch))) return; NVIC_DisableIRQ(UART2_IRQn); NVIC_DisableIRQ(UART0_IRQn); if(touch > 23 && (par[0]-48)) { sprintf(buf_tx,"ERROR %u",ERROR_PARAMETER); return; } if(par[0] - 48) /*Transforma em inteiro*/ { /*Desliga led anterior (IRs) caso ainda esteja ligado*/ for(i=TOUCH_0;i<=TOUCH_23;i++) { if(i == TOUCH_11 && !ir_state.bit.PwrPainel) out_leds |= (1<<TOUCH_11); else out_leds &= ~(1 << i); } touch_led_press = touch; out_leds |= (1 << touch_led_press); atualiza_saidas(); if(rcv_cmd != RCV_CMD_TCP_CLIENT && rcv_cmd != RCV_CMD_TCP_SERVER) beep(BEEP_PULSO); /*(TV)->ID0:Source...ID1:CH-...ID2:CH+...ID3:ON...ID4:OFF...ID5:Vol-...ID6:Vol+*/ /*(HOME)->ID7:Source...ID8:VOL-...ID9:VOL+...ID10:ON...ID11:OFF...ID12:PLAY...ID13:PAUSE...ID14:BACK...ID15:NEXT*/ /*ID16: Cursor Left...ID17: Cursor Righ...ID18: Cursor Down*/ /*(AR)->ID19:16°...ID20:17°............ID33:30°...ID34:ON...ID35:OFF..ID36:SWING ON..ID37:SWING OFF*/ if(touch == TOUCH_0) /*Touch referente ao Power da TV*/ { if(!ir_state.bit.PwrTv)strcpy(str_IdIr,ADDR_TV_ON); /*IR power tv on*/ else strcpy(str_IdIr,ADDR_TV_OFF); /*IR power tv off*/ ir_state.bit.PwrTv = !ir_state.bit.PwrTv; sprintf(str_aux,"[Touch (%u) POWER %s TV]\r",touch,(ir_state.bit.PwrTv) ? "ON":"OFF"); /*String para debug*/ }else if(touch == TOUCH_1) /*Touch referente ao Source da TV*/ { strcpy(str_IdIr,ADDR_TV_SCR); /*IR source tv*/ sprintf(str_aux,"[SOURCE TV]\r"); /*String para debug*/ }else if(touch == TOUCH_2) /*Touch referente ao CH- da TV*/ { strcpy(str_IdIr,ADDR_TV_CH_DOWN); /*IR ch- tv*/ sprintf(str_aux,"[CH- TV]\r"); /*String para debug*/ }else if(touch == TOUCH_3) /*Touch referente ao CH+ da TV*/ { strcpy(str_IdIr,ADDR_TV_CH_UP); /*IR ch+ tv*/ sprintf(str_aux,"[CH+ TV]\r"); /*String para debug*/ }else if(touch == TOUCH_4) /*Touch referente ao Power Home*/ { if(!ir_state.bit.PwrHome)strcpy(str_IdIr,ADDR_HOME_ON); /*IR Power home on*/ else strcpy(str_IdIr,ADDR_HOME_OFF); /*IR Power home off*/ ir_state.bit.PwrHome = !ir_state.bit.PwrHome; sprintf(str_aux,"[POWER %s HOME]\r",(ir_state.bit.PwrHome) ? "ON":"OFF"); /*String para debug*/ }else if(touch == TOUCH_5) /*Touch referente ao Source do Home*/ { strcpy(str_IdIr,ADDR_HOME_SCR); /*IR source home*/ sprintf(str_aux,"[SOURCE HOME]\r"); /*String para debug*/ }else if(touch == TOUCH_6) /*Touch referente ao Volume- da Tv*/ { strcpy(str_IdIr,ADDR_TV_VOL_DOWN); /*IR vol- tv*/ sprintf(str_aux,"[VOL- TV]\r"); /*String para debug*/ /*Envia repetidamente o IR apenas se pressionar no teclado. Pelo software executa o IR apenas uma vez*/ if(rcv_cmd == RCV_CMD_UART_2) { repeat_IR(str_IdIr,0,5); /*ID, Intervalo de repetição(n*100ms) e Intervalo start(ms)*/ flag_send_ir = __FALSE; } }else if(touch == TOUCH_7) /*Touch referente ao Volume+ da Tv*/ { strcpy(str_IdIr,ADDR_TV_VOL_UP); /*IR vol+ tv*/ sprintf(str_aux,"[VOL+ TV]\r"); /*String para debug*/ /*Envia repetidamente o IR apenas se pressionar no teclado. Pelo software executa o IR apenas uma vez*/ if(rcv_cmd == RCV_CMD_UART_2) { repeat_IR(str_IdIr,0,5); /*ID, Intervalo de repetição(n*100ms) e Intervalo start(ms)*/ flag_send_ir = __FALSE; } }else if(touch == TOUCH_8) /*Touch referente ao cursor Left do Home*/ { strcpy(str_IdIr,ADDR_HOME_LEFT); /*IR left home*/ sprintf(str_aux,"[LEFT HOME]\r"); /*String para debug*/ /*Envia repetidamente o IR apenas se pressionar no teclado. Pelo software executa o IR apenas uma vez*/ if(rcv_cmd == RCV_CMD_UART_2) { repeat_IR(str_IdIr,0,5); /*ID, Intervalo de repetição(n*100ms) e Intervalo start(ms)*/ flag_send_ir = __FALSE; } ir_state.bit.PlayPause = __FALSE; /*Deixa a tecla Play/Pause preparada para enviar o play caso pressionada*/ }else if(touch == TOUCH_9) /*Touch referente ao cursor Righ do Home*/ { strcpy(str_IdIr,ADDR_HOME_RIGH); /*IR righ home*/ sprintf(str_aux,"[RIGH HOME]\r"); /*String para debug*/ /*Envia repetidamente o IR apenas se pressionar no teclado. Pelo software executa o IR apenas uma vez*/ if(rcv_cmd == RCV_CMD_UART_2) { repeat_IR(str_IdIr,0,5); /*ID, Intervalo de repetição(n*100ms) e Intervalo start(ms)*/ flag_send_ir = __FALSE; } ir_state.bit.PlayPause = __FALSE; /*Deixa a tecla Play/Pause preparada para enviar o play caso pressionada*/ }else if(touch == TOUCH_10) /*Touch referente ao Volume- do Home*/ { strcpy(str_IdIr,ADDR_HOME_VOL_DOWN); /*IR vol- home*/ sprintf(str_aux,"[VOL- HOME]\r"); /*String para debug*/ /*Envia repetidamente o IR apenas se pressionar no teclado. Pelo software executa o IR apenas uma vez*/ if(rcv_cmd == RCV_CMD_UART_2) { repeat_IR(str_IdIr,0,5); /*ID, Intervalo de repetição(n*100ms) e Intervalo start(ms)*/ flag_send_ir = __FALSE; } }else if(touch == TOUCH_11) /*Touch referente ao Volume+ do Home*/ { strcpy(str_IdIr,ADDR_HOME_VOL_UP); /*IR vol+ home*/ sprintf(str_aux,"[VOL+ HOME]\r"); /*String para debug*/ /*Envia repetidamente o IR apenas se pressionar no teclado. Pelo software executa o IR apenas uma vez*/ if(rcv_cmd == RCV_CMD_UART_2) { repeat_IR(str_IdIr,0,5); /*ID, Intervalo de repetição(n*100ms) e Intervalo start(ms)*/ flag_send_ir = __FALSE; } }else if(touch == TOUCH_12) /*Touch referente ao cursor Down do home*/ { strcpy(str_IdIr,ADDR_HOME_DOWN); /*IR down home*/ sprintf(str_aux,"[DOWN HOME]\r"); /*String para debug*/ /*Envia repetidamente o IR apenas se pressionar no teclado. Pelo software executa o IR apenas uma vez*/ if(rcv_cmd == RCV_CMD_UART_2) { repeat_IR(str_IdIr,0,5); /*ID, Intervalo de repetição(n*100ms) e Intervalo start(ms)*/ flag_send_ir = __FALSE; } ir_state.bit.PlayPause = __FALSE; /*Deixa a tecla Play/Pause preparada para enviar o play caso pressionada*/ }else if(touch == TOUCH_13) /*Touch referente ao Play/Pause do Home*/ { if(!ir_state.bit.PlayPause)strcpy(str_IdIr,ADDR_HOME_PLAY); /*IR play*/ else strcpy(str_IdIr,ADDR_HOME_PAUSE); /*IR pause*/ ir_state.bit.PlayPause = !ir_state.bit.PlayPause; sprintf(str_aux,"[%s HOME]\r",(ir_state.bit.PlayPause)? "PLAY":"PAUSE"); /*String para debug*/ }else if(touch == TOUCH_14) /*Touch referente ao Back do home*/ { strcpy(str_IdIr,ADDR_HOME_BACK); /*IR back home*/ sprintf(str_aux,"[BACK HOME]\r"); /*String para debug*/ }else if(touch == TOUCH_15) /*Touch referente ao Next do Home*/ { strcpy(str_IdIr,ADDR_HOME_NEXT); /*IR next home*/ sprintf(str_aux,"[NEXT HOME]\r"); /*String para debug*/ }else if(touch == TOUCH_17) /*Touch referente ao Power do AR*/ { if(!ir_state.bit.PwrAr)strcpy(str_IdIr,ADDR_AR_PWR_ON); /*IR power ar on*/ else strcpy(str_IdIr,ADDR_AR_PWR_OFF); /*IR power ar off*/ ir_state.bit.PwrAr = !ir_state.bit.PwrAr; sprintf(str_aux,"[%s] [SWING %s] [IR ID:%s] [POWER %s AR]\r",(atoi(cfg.file.mode_func_ar))? "IN":"OUT", (ir_state.bit.ArSwing)? "ON":"OFF", str_IdIr, (ir_state.bit.PwrAr) ? "ON":"OFF"); /*String para debug*/ }else if(touch == TOUCH_19 || touch == TOUCH_21 || touch == TOUCH_23) { if(touch == TOUCH_19) { if(temp_ar < TEMPERATURA_MAX) temp_ar++; sprintf(str_IdIr,"%u\0",temp_ar + 3); /*IR temp*/ }else if(touch == TOUCH_21) { if(temp_ar > TEMPERATURA_MIN) temp_ar--; sprintf(str_IdIr,"%u\0",temp_ar + 3); /*IR temp*/ }else if(touch == TOUCH_23) { ir_state.bit.ArSwing = !ir_state.bit.ArSwing; /*IR swing ar*/ if(atoi(cfg.file.mode_func_ar)) /*Swing In (Função swing embutida na temperatura)?*/ sprintf(str_IdIr,"%u\0",temp_ar + 3); else { if(!ir_state.bit.ArSwing)strcpy(str_IdIr,ADDR_AR_SWING_ON); /*Endereço Swing On*/ else strcpy(str_IdIr,ADDR_AR_SWING_OFF); /*Endereço Swing Off*/ } } sprintf(str_aux,"[%s] [SWING %s] [IR ID:%s] [TEMP %u°]\r",(atoi(cfg.file.mode_func_ar))? "IN":"OUT", (ir_state.bit.ArSwing)? "ON":"OFF", str_IdIr, temp_ar); /*String para debug*/ }else { /*nenhuma função para o touch recebido*/ return; } if(flag_send_ir) /*Precisa enviar IR?*/ { cmd_ir_send(str_IdIr); /*Chama função que envia o ir cujo id do ir é pasado como parâmetro*/ if(buf_tx[0] == 'E') /*Houve algum erro ao enviar o IR?*/ { beep(BEEP_ERROR); strcat(buf_tx,"\r\r\0"); uart_putString(0,buf_tx); }else { /*Sem erros*/ //strcat(str_aux,"\r\0"); //uart_putString(0,str_aux); //printf("[Touch:%u] [IR ID:%s] %s\r",touch, str_IdIr, str_aux); //fflush(stdout); sprintf(buf_tx,"OK %u",touch); } printf("[Touch:%u] [IR ID:%s] %s\r",touch, str_IdIr, str_aux); fflush(stdout); }else { // strcat(str_aux,"\r\0"); // uart_putString(0,str_aux); printf("[Touch:%u] [IR ID:%s] %s\r",touch, str_IdIr, str_aux); fflush(stdout); } }else { for(i=TOUCH_0;i<=TOUCH_23;i++) /*Loop para desligar todos os leds 4x4*/ out_leds &= ~(1<<i); touch_led_press = TOUCH_NONE; } }
/** * @brief Disables a device specific interrupt in the NVIC interrupt controller. * @param IRQn External interrupt number . * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { /* Disable interrupt */ NVIC_DisableIRQ(IRQn); }
/*---------------------------------------------------------------------------------------------------------*/ int32_t main(void) { uint32_t i; /* Unlock protected registers */ SYS_UnlockReg(); /* Init System, IP clock and multi-function I/O */ SYS_Init(); /* Init UART0 for printf */ UART0_Init(); /* Lock protected registers */ SYS_LockReg();; /* This sample code is I2C SLAVE mode and it simulates EEPROM function */ printf("\n"); printf("+---------------------------------------------------------------------------+\n"); printf("| NUC029xEE I2C Driver Sample Code (Slave) for wake-up & access Slave test |\n"); printf("| |\n"); printf("| I2C Master (I2C0) <---> I2C Slave(I2C0) |\n"); printf("+---------------------------------------------------------------------------+\n"); printf("Configure I2C0 as a slave.\n"); printf("The I/O connection for I2C0:\n"); printf("I2C0_SDA(PA.8), I2C0_SCL(PA.9)\n"); /* Init I2C0 */ I2C0_Init(); for(i = 0; i < 0x100; i++) { g_au8SlvData[i] = 0; } /* I2C function to Transmit/Receive data as slave */ s_I2C0HandlerFn = I2C_SlaveTRx; /* Set I2C0 enter Not Address SLAVE mode */ I2C_SET_CONTROL_REG(I2C0, I2C_I2CON_SI_AA); /* Unlock protected registers */ SYS_UnlockReg(); /* Enable power wake-up interrupt */ CLK->PWRCON |= CLK_PWRCON_PD_WU_INT_EN_Msk; NVIC_EnableIRQ(PWRWU_IRQn); /* Enable I2C wake-up */ I2C0-> I2CWKUPCON |= I2C_I2CWKUPCON_WKUPEN_Msk; /* Enable Chip enter power down mode */ CLK->PWRCON |= CLK_PWRCON_PD_WAIT_CPU_Msk; /* Processor use deep sleep */ SCB->SCR = SCB_SCR_SLEEPDEEP_Msk; /* System power down enable */ CLK->PWRCON |= CLK_PWRCON_PWR_DOWN_EN_Msk; printf("\n"); printf("Enter PD 0x%x 0x%x\n", I2C0->I2CON , I2C0->I2CSTATUS); printf("\n"); printf("CHIP enter power down status.\n"); /* Waiting for UART printf finish*/ while(((UART0->FSR) & UART_FSR_TE_FLAG_Msk) == 0); if(((I2C0->I2CON)&I2C_I2CON_SI_Msk) != 0) { I2C_SET_CONTROL_REG(I2C0, I2C_I2CON_SI); } /* Use WFI instruction to idle the CPU. NOTE: If ICE is attached, system will wakeup immediately because ICE is a wakeup event. */ __WFI(); __NOP(); __NOP(); __NOP(); while((g_u8SlvPWRDNWK & g_u8SlvI2CWK) == 0); printf("Power-down Wake-up INT 0x%x\n", ((CLK->PWRCON) & CLK_PWRCON_PD_WU_STS_Msk)); printf("I2C0 WAKE INT 0x%x\n", I2C0->I2CWKUPSTS); /* Disable power wake-up interrupt */ CLK->PWRCON &= ~CLK_PWRCON_PD_WU_INT_EN_Msk; NVIC_DisableIRQ(PWRWU_IRQn); /* Lock protected registers */ SYS_LockReg(); printf("\n"); printf("Slave wake-up from power down status.\n"); printf("\n"); printf("Slave Waiting for receiving data.\n"); while(1); }
OSStatus platform_uart_deinit( platform_uart_driver_t* driver ) { uint8_t uart_number; OSStatus err = kNoErr; platform_mcu_powersave_disable(); require_action_quiet( ( driver != NULL ), exit, err = kParamErr); uart_number = platform_uart_get_port_number( driver->peripheral->port ); /* Disable USART */ USART_Cmd( driver->peripheral->port, DISABLE ); /* Deinitialise USART */ USART_DeInit( driver->peripheral->port ); /************************************************************************** * De-initialise STM32 DMA and interrupt **************************************************************************/ /* Deinitialise DMA streams */ DMA_DeInit( driver->peripheral->tx_dma_config.stream ); DMA_DeInit( driver->peripheral->rx_dma_config.stream ); /* Disable TC (transfer complete) interrupt at the source */ DMA_ITConfig( driver->peripheral->tx_dma_config.stream, DMA_INTERRUPT_FLAGS, DISABLE ); DMA_ITConfig( driver->peripheral->rx_dma_config.stream, DMA_INTERRUPT_FLAGS, DISABLE ); /* Disable transmit DMA interrupt at Cortex-M3 */ NVIC_DisableIRQ( driver->peripheral->tx_dma_config.irq_vector ); /************************************************************************** * De-initialise STM32 USART interrupt **************************************************************************/ USART_ITConfig( driver->peripheral->port, USART_IT_RXNE, DISABLE ); /* Disable UART interrupt vector on Cortex-M3 */ NVIC_DisableIRQ( driver->peripheral->rx_dma_config.irq_vector ); /* Disable registers clocks */ uart_peripheral_clock_functions[uart_number]( uart_peripheral_clocks[uart_number], DISABLE ); #ifndef NO_MICO_RTOS mico_rtos_deinit_semaphore( &driver->rx_complete ); mico_rtos_deinit_semaphore( &driver->tx_complete ); mico_rtos_deinit_mutex( &driver->tx_mutex ); #else driver->rx_complete = false; driver->tx_complete = false; #endif driver->rx_size = 0; driver->tx_size = 0; driver->last_transmit_result = kNoErr; driver->last_receive_result = kNoErr; exit: platform_mcu_powersave_enable(); return err; }
static int usart_configure_as_uart (sBSPACMperiphUARTstate * usp, const sBSPACMperiphUARTconfiguration * cfgp) { USART_TypeDef * usart; const sBSPACMdeviceEFM32periphUARTdevcfg * devcfgp; if (! (usp && usp->uart)) { return -1; } usart = (USART_TypeDef *)usp->uart; /* For a USART the devcfgp object is actual a * sBSPACMdeviceEFM32periphUSARTdevcfg, but that structure simply * extends the UART part of the configuration. */ devcfgp = (const sBSPACMdeviceEFM32periphUARTdevcfg *)usp->devcfg.ptr; /* If enabling configuration, enable the high-frequency peripheral * clock and the clock for the uart itself. * * If disabling configuration, disable the interrupts. */ if (cfgp) { CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(devcfgp->common.clock, true); } else { NVIC_DisableIRQ(devcfgp->rx_irqn); NVIC_DisableIRQ(devcfgp->tx_irqn); NVIC_ClearPendingIRQ(devcfgp->rx_irqn); NVIC_ClearPendingIRQ(devcfgp->tx_irqn); } USART_Reset(usart); if (usp->rx_fifo_ni_) { fifo_reset(usp->rx_fifo_ni_); } if (usp->tx_fifo_ni_) { fifo_reset(usp->tx_fifo_ni_); } usp->tx_state_ = 0; if (cfgp) { unsigned int baud_rate = cfgp->speed_baud; if (0 == baud_rate) { baud_rate = 115200; } /* Configure the USART for 8N1. Set TXBL at half-full. */ usart->FRAME = USART_FRAME_DATABITS_EIGHT | USART_FRAME_PARITY_NONE | USART_FRAME_STOPBITS_ONE; usart->CTRL |= USART_CTRL_TXBIL_HALFFULL; USART_BaudrateAsyncSet(usart, 0, baud_rate, usartOVS16); CMU_ClockEnable(cmuClock_GPIO, true); } else { /* Done with device; turn it off */ CMU_ClockEnable(devcfgp->common.clock, false); } /* Enable or disable UART pins. To avoid false start, when enabling * configure TX as high. This relies on a comment in the EMLIB code * that manipulating registers of disabled modules has no effect * (unlike TM4C where it causes a HardFault). We'll see. */ vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.rx_pinmux, !!cfgp, 1); vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.tx_pinmux, !!cfgp, 0); if (cfgp) { usart->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | devcfgp->common.location; /* Clear and enable RX interrupts. TX interrupts are enabled at the * peripheral when there's something to transmit. TX and RX are * enabled at the NVIC now. */ usart->IFC = _USART_IF_MASK; usart->IEN = USART_IF_RXDATAV; NVIC_ClearPendingIRQ(devcfgp->rx_irqn); NVIC_ClearPendingIRQ(devcfgp->tx_irqn); NVIC_EnableIRQ(devcfgp->rx_irqn); NVIC_EnableIRQ(devcfgp->tx_irqn); /* Configuration complete; enable the USART */ usart->CMD = USART_CMD_RXEN | USART_CMD_TXEN; } return 0; }
void dbg_setup_uart_default(uint32_t baudrate) { uint32_t fDiv; uint32_t regVal; NVIC_DisableIRQ(UART_IRQn); /* Set 1.6 UART RXD */ IOCON_PIO1_6 &= ~IOCON_PIO1_6_FUNC_MASK; IOCON_PIO1_6 |= IOCON_PIO1_6_FUNC_UART_RXD; /* Set 1.7 UART TXD */ IOCON_PIO1_7 &= ~IOCON_PIO1_7_FUNC_MASK; IOCON_PIO1_7 |= IOCON_PIO1_7_FUNC_UART_TXD; /* Enable UART clock */ SCB_SYSAHBCLKCTRL |= (SCB_SYSAHBCLKCTRL_UART); SCB_UARTCLKDIV = SCB_UARTCLKDIV_DIV1; /* divided by 1 */ /* 8 bits, no Parity, 1 Stop bit */ UART_U0LCR = (UART_U0LCR_Word_Length_Select_8Chars | UART_U0LCR_Stop_Bit_Select_1Bits | UART_U0LCR_Parity_Disabled | UART_U0LCR_Parity_Select_OddParity | UART_U0LCR_Break_Control_Disabled | UART_U0LCR_Divisor_Latch_Access_Enabled); /* Baud rate */ regVal = SCB_UARTCLKDIV; fDiv = (((CFG_CPU_CCLK * SCB_SYSAHBCLKDIV)/regVal)/16)/baudrate; UART_U0DLM = fDiv / 256; UART_U0DLL = fDiv % 256; /* Set DLAB back to 0 */ UART_U0LCR = (UART_U0LCR_Word_Length_Select_8Chars | UART_U0LCR_Stop_Bit_Select_1Bits | UART_U0LCR_Parity_Disabled | UART_U0LCR_Parity_Select_OddParity | UART_U0LCR_Break_Control_Disabled | UART_U0LCR_Divisor_Latch_Access_Disabled); /* Enable and reset TX and RX FIFO. */ UART_U0FCR = (UART_U0FCR_FIFO_Enabled | UART_U0FCR_Rx_FIFO_Reset | UART_U0FCR_Tx_FIFO_Reset); /* Read to clear the line status. */ regVal = UART_U0LSR; /* Ensure a clean start, no data in either TX or RX FIFO. */ while (( UART_U0LSR & (UART_U0LSR_THRE|UART_U0LSR_TEMT)) != (UART_U0LSR_THRE|UART_U0LSR_TEMT) ); while ( UART_U0LSR & UART_U0LSR_RDR_DATA ) { /* Dump data from RX FIFO */ regVal = UART_U0RBR; } /* Enable the UART Interrupt */ NVIC_EnableIRQ(UART_IRQn); UART_U0IER = UART_U0IER_RBR_Interrupt_Enabled | UART_U0IER_RLS_Interrupt_Enabled; return; }
static int leuart_configure (sBSPACMperiphUARTstate * usp, const sBSPACMperiphUARTconfiguration * cfgp) { LEUART_TypeDef * leuart; const sBSPACMdeviceEFM32periphLEUARTdevcfg * devcfgp; if (! (usp && usp->uart)) { return -1; } leuart = (LEUART_TypeDef *)usp->uart; devcfgp = (const sBSPACMdeviceEFM32periphLEUARTdevcfg *)usp->devcfg.ptr; /* Configure LFB's source, enable the low-energy peripheral clock, and the clock for the * leuart itself */ if (cfgp) { /* LFB is required for LEUART. Power-up is LFRCO which doesn't * work so good; if we were told a source to use, override * whatever was there. */ if (devcfgp->lfbsel) { CMU_ClockSelectSet(cmuClock_LFB, devcfgp->lfbsel); } CMU_ClockEnable(cmuClock_CORELE, true); CMU_ClockEnable(devcfgp->common.clock, true); } else { NVIC_DisableIRQ(devcfgp->irqn); NVIC_ClearPendingIRQ(devcfgp->irqn); } LEUART_Reset(leuart); leuart->FREEZE = LEUART_FREEZE_REGFREEZE; leuart->CMD = LEUART_CMD_RXDIS | LEUART_CMD_TXDIS; if (usp->rx_fifo_ni_) { fifo_reset(usp->rx_fifo_ni_); } if (usp->tx_fifo_ni_) { fifo_reset(usp->tx_fifo_ni_); } usp->tx_state_ = 0; if (cfgp) { unsigned int speed_baud = cfgp->speed_baud; if (0 == speed_baud) { speed_baud = 9600; } /* Configure the LEUART for rate at 8N1. */ leuart->CTRL = LEUART_CTRL_DATABITS_EIGHT | LEUART_CTRL_PARITY_NONE | LEUART_CTRL_STOPBITS_ONE; LEUART_BaudrateSet(leuart, 0, speed_baud); CMU_ClockEnable(cmuClock_GPIO, true); } /* Enable or disable UART pins. To avoid false start, when enabling * configure TX as high. This relies on a comment in the EMLIB code * that manipulating registers of disabled modules has no effect * (unlike TM4C where it causes a HardFault). We'll see. */ vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.rx_pinmux, !!cfgp, 1); vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.tx_pinmux, !!cfgp, 0); if (cfgp) { leuart->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | devcfgp->common.location; /* Clear and enable RX interrupts at the device. Device TX * interrupts are enabled at the peripheral when there's something * to transmit. Clear then enable interrupts at the NVIC. */ leuart->IFC = _LEUART_IF_MASK; leuart->IEN = LEUART_IF_RXDATAV; NVIC_ClearPendingIRQ(devcfgp->irqn); NVIC_EnableIRQ(devcfgp->irqn); /* Configuration complete; enable the LEUART, and release the * registers to synchronize. */ leuart->CMD = LEUART_CMD_RXEN | LEUART_CMD_TXEN; leuart->FREEZE = 0; } else { CMU_ClockEnable(devcfgp->common.clock, false); } return 0; }
static hBSPACMperiphUART spi_configure (sBSPACMperiphUARTstate * usp, const sBSPACMperiphUARTconfiguration * cfgp) { USART_TypeDef * usart; const sBSPACMdeviceEFM32periphUSARTdevcfg * devcfgp; if (! (usp && usp->uart)) { return NULL; } usart = (USART_TypeDef *)usp->uart; devcfgp = (const sBSPACMdeviceEFM32periphUSARTdevcfg *)usp->devcfg.ptr; /* If enabling configuration, enable the high-frequency peripheral * clock and the clock for the uart itself. * * If disabling configuration, disable the interrupts. */ if (cfgp) { CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(devcfgp->uart.common.clock, true); } else { NVIC_DisableIRQ(devcfgp->uart.rx_irqn); NVIC_DisableIRQ(devcfgp->uart.tx_irqn); NVIC_ClearPendingIRQ(devcfgp->uart.rx_irqn); NVIC_ClearPendingIRQ(devcfgp->uart.tx_irqn); } USART_Reset(usart); if (usp->rx_fifo_ni_) { fifo_reset(usp->rx_fifo_ni_); } if (usp->tx_fifo_ni_) { fifo_reset(usp->tx_fifo_ni_); } usp->tx_state_ = 0; if (cfgp) { /* Setting baudrate */ usart->CLKDIV = 128 * (SystemCoreClock / 1000000UL - 2); /* Configure USART */ /* Using synchronous (USART) mode, MSB first */ usart->CTRL = USART_CTRL_SYNC | USART_CTRL_MSBF; // NOT AUTOCS // usart->CTRL |= USART_CTRL_AUTOCS /* Clearing old transfers/receptions, and disabling interrupts */ usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; usart->IEN = 0; /* Enabling Master, TX and RX */ CMU_ClockEnable(cmuClock_GPIO, true); } else { /* Done with device; turn it off */ CMU_ClockEnable(devcfgp->uart.common.clock, false); } /* Enable or disable UART pins. To avoid false start, when enabling * configure TX as high. This relies on a comment in the EMLIB code * that manipulating registers of disabled modules has no effect * (unlike TM4C where it causes a HardFault). We'll see. */ vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->uart.common.rx_pinmux, !!cfgp, 0); vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->uart.common.tx_pinmux, !!cfgp, 0); vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->clk_pinmux, !!cfgp, 0); vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->cs_pinmux, !!cfgp, 1); if (cfgp) { /* Enabling pins and setting location */ usart->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN | USART_ROUTE_CSPEN | devcfgp->uart.common.location; /* Clear and enable RX interrupts. TX interrupts are enabled at the * peripheral when there's something to transmit. TX and RX are * enabled at the NVIC now. */ usart->IFC = _USART_IF_MASK; //usart->IEN = USART_IF_RXDATAV; NVIC_ClearPendingIRQ(devcfgp->uart.rx_irqn); NVIC_ClearPendingIRQ(devcfgp->uart.tx_irqn); NVIC_EnableIRQ(devcfgp->uart.rx_irqn); NVIC_EnableIRQ(devcfgp->uart.tx_irqn); /* Configuration complete; enable the USART */ usart->CMD = USART_CMD_MASTEREN | USART_CMD_TXEN | USART_CMD_RXEN; } return usp; }
/*..........................................................................*/ uint8_t QS_onStartup(void const *arg) { static uint8_t qsBuf[QS_BUF_SIZE]; /* buffer for Quantum Spy */ QS_initBuf(qsBuf, sizeof(qsBuf)); UARTInit(QS_BAUD_RATE); /*initialize the UART with the desired baud rate*/ NVIC_DisableIRQ(UART_IRQn);/*do not use the interrupts (QS uses polling)*/ LPC_UART->IER = 0; QS_tickPeriod_ = (QSTimeCtr)(SystemCoreClock / BSP_TICKS_PER_SEC); QS_tickTime_ = QS_tickPeriod_; /* to start the timestamp at zero */ /* setup the QS filters... */ QS_FILTER_ON(QS_ALL_RECORDS); // QS_FILTER_OFF(QS_QEP_STATE_EMPTY); // QS_FILTER_OFF(QS_QEP_STATE_ENTRY); // QS_FILTER_OFF(QS_QEP_STATE_EXIT); // QS_FILTER_OFF(QS_QEP_STATE_INIT); // QS_FILTER_OFF(QS_QEP_INIT_TRAN); // QS_FILTER_OFF(QS_QEP_INTERN_TRAN); // QS_FILTER_OFF(QS_QEP_TRAN); // QS_FILTER_OFF(QS_QEP_IGNORED); QS_FILTER_OFF(QS_QF_ACTIVE_ADD); QS_FILTER_OFF(QS_QF_ACTIVE_REMOVE); QS_FILTER_OFF(QS_QF_ACTIVE_SUBSCRIBE); QS_FILTER_OFF(QS_QF_ACTIVE_UNSUBSCRIBE); QS_FILTER_OFF(QS_QF_ACTIVE_POST_FIFO); QS_FILTER_OFF(QS_QF_ACTIVE_POST_LIFO); QS_FILTER_OFF(QS_QF_ACTIVE_GET); QS_FILTER_OFF(QS_QF_ACTIVE_GET_LAST); QS_FILTER_OFF(QS_QF_EQUEUE_INIT); QS_FILTER_OFF(QS_QF_EQUEUE_POST_FIFO); QS_FILTER_OFF(QS_QF_EQUEUE_POST_LIFO); QS_FILTER_OFF(QS_QF_EQUEUE_GET); QS_FILTER_OFF(QS_QF_EQUEUE_GET_LAST); QS_FILTER_OFF(QS_QF_MPOOL_INIT); QS_FILTER_OFF(QS_QF_MPOOL_GET); QS_FILTER_OFF(QS_QF_MPOOL_PUT); QS_FILTER_OFF(QS_QF_PUBLISH); QS_FILTER_OFF(QS_QF_NEW); QS_FILTER_OFF(QS_QF_GC_ATTEMPT); QS_FILTER_OFF(QS_QF_GC); // QS_FILTER_OFF(QS_QF_TICK); QS_FILTER_OFF(QS_QF_TIMEEVT_ARM); QS_FILTER_OFF(QS_QF_TIMEEVT_AUTO_DISARM); QS_FILTER_OFF(QS_QF_TIMEEVT_DISARM_ATTEMPT); QS_FILTER_OFF(QS_QF_TIMEEVT_DISARM); QS_FILTER_OFF(QS_QF_TIMEEVT_REARM); QS_FILTER_OFF(QS_QF_TIMEEVT_POST); QS_FILTER_OFF(QS_QF_CRIT_ENTRY); QS_FILTER_OFF(QS_QF_CRIT_EXIT); QS_FILTER_OFF(QS_QF_ISR_ENTRY); QS_FILTER_OFF(QS_QF_ISR_EXIT); // QS_FILTER_OFF(QS_QK_MUTEX_LOCK); // QS_FILTER_OFF(QS_QK_MUTEX_UNLOCK); QS_FILTER_OFF(QS_QK_SCHEDULE); return (uint8_t)1; /* return success */ }
/** * * @brief Disable an interrupt line * * Disable an interrupt line. After this call, the CPU will stop receiving * interrupts for the specified <irq>. * * @return N/A */ void z_arch_irq_disable(unsigned int irq) { NVIC_DisableIRQ((IRQn_Type)irq); }
void sendAddresses() { NVIC_DisableIRQ(USB_IRQn); CDC_WriteInEp(&addresses, sizeof(addresses)); NVIC_EnableIRQ(USB_IRQn); }
void stop_trainer_capture() { TRAINER_TIMER->CR1 &= ~TIM_CR1_CEN ; // Stop counter TRAINER_TIMER->DIER = 0; // Stop Interrupt NVIC_DisableIRQ(TRAINER_TIMER_IRQn) ; // Stop Interrupt }
void uart_write(uart_t uart, const uint8_t *data, size_t len) { switch(uart) { #if UART_0_EN case UART_0: #if UART_0_ENABLE_BUF for(int count = 0; count < len; count++) { NVIC_DisableIRQ(UART_0_IRQ_TX_CHAN); ringbuffer_add_one(&rb_uart0, data[count]); NVIC_EnableIRQ(UART_0_IRQ_TX_CHAN); } USART_IntEnable(UART_0_DEV, USART_IF_TXBL); #else for(size_t i = 0; i < len; i++) { /* Check that transmit buffer is empty */ while(!(UART_0_DEV->STATUS & USART_STATUS_TXBL)) ; /* Write data to buffer */ UART_0_DEV->TXDATA = (uint32_t)data[i]; } #endif break; #endif #if UART_1_EN case UART_1: #if UART_1_ENABLE_BUF for(int count = 0; count < len; count++) { NVIC_DisableIRQ(UART_1_IRQ_TX_CHAN); ringbuffer_add_one(&rb_uart1, data[count]); NVIC_EnableIRQ(UART_1_IRQ_TX_CHAN); } USART_IntEnable(UART_1_DEV, USART_IF_TXBL); #else for(size_t i = 0; i < len; i++) { /* Check that transmit buffer is empty */ while(!(UART_1_DEV->STATUS & USART_STATUS_TXBL)) ; /* Write data to buffer */ UART_1_DEV->TXDATA = (uint32_t)data[i]; } #endif break; #endif #if UART_2_EN case UART_2: #if UART_2_ENABLE_BUF for(int count = 0; count < len; count++) { NVIC_DisableIRQ(UART_2_IRQ); ringbuffer_add_one(&rb_uart2, data[count]); NVIC_EnableIRQ(UART_2_IRQ); } LEUART_IntEnable(UART_2_DEV, LEUART_IF_TXBL); #else for(size_t i = 0; i < len; i++) { /* Check that transmit buffer is empty */ while (!(UART_2_DEV->STATUS & LEUART_STATUS_TXBL)) ; /* Avoid deadlock if modifying the same register twice when freeze mode is */ /* activated. */ if (!(UART_2_DEV->FREEZE & LEUART_FREEZE_REGFREEZE)) { /* Wait for any pending previous write operation to have been completed */ /* in low frequency domain */ while (UART_2_DEV->SYNCBUSY & LEUART_SYNCBUSY_TXDATA); ; UART_2_DEV->TXDATA = (uint32_t)data[i]; } } #endif break; #endif } }
void DEBUG_UART_Stop() { CONSOLE_USART->UART_IDR = UART_IDR_RXRDY ; NVIC_DisableIRQ(UART0_IRQn) ; }
void DeinitCAN(){ NVIC_DisableIRQ(CAN_IRQn); }
/* ser_phy API function */ void ser_phy_interrupts_disable(void) { NVIC_DisableIRQ(UART0_IRQn); return; }
/***************************************************************************** ** Function name: RS485Init ** ** Descriptions: Initialize UART0 port, setup pin select, ** clock, parity, stop bits, FIFO, etc. ** ** parameters: UART baudrate ** Returned value: None ** *****************************************************************************/ void RS485Init(uint32_t baudrate) { uint32_t Fdiv; uint32_t regVal; UARTCount = 0; NVIC_DisableIRQ(UART_IRQn); LPC_IOCON->PIO1_6 &= ~0x07; /* UART I/O config */ LPC_IOCON->PIO1_6 |= 0x01; /* UART RXD */ LPC_IOCON->PIO1_7 &= ~0x07; LPC_IOCON->PIO1_7 |= 0x01; /* UART TXD */ /* Enable UART clock */ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */ LPC_UART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ regVal = LPC_SYSCON->UARTCLKDIV; Fdiv = (((SystemFrequency/LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate; /*baud rate */ LPC_UART->DLM = Fdiv / 256; LPC_UART->DLL = Fdiv % 256; LPC_UART->LCR = 0x03; /* DLAB = 0 */ LPC_UART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ /* Read to clear the line status. */ regVal = LPC_UART->LSR; /* Ensure a clean start, no data in either TX or RX FIFO. */ while ( LPC_UART->LSR & (LSR_THRE|LSR_TEMT) != (LSR_THRE|LSR_TEMT) ); while ( LPC_UART->LSR & LSR_RDR ) { regVal = LPC_UART->RBR; /* Dump data from RX FIFO */ } LPC_UART->LCR |= ((0x3<<4)|(0x1<<3)); /* forced "0" sticky parity, parity enable */ LPC_UART->ADRMATCH = RS485_SLAVE_ADR; /* UARTA 485 address, 0xC0 */ #if RS485_NMM LPC_UART->RS485CTRL = RS485_NMMEN; /* NMM mode */ #else LPC_UART->RS485CTRL = RS485_NMMEN|RS485_AADEN|RS485_RXDIS; /* AAD mode */ #endif /* Below is the direction control setting. */ #if DIR_CTRL /* Either DTR or RTS can be used as direction pin out. */ #if 1 LPC_IOCON->PIO1_5 &= ~0x07; LPC_IOCON->PIO1_5 |= 0x01; /* UART_DIR or UART_RTS(HB1) as direction control. */ LPC_UART->RS485CTRL |= RS485_DCTRL; #else LPC_IOCON->PIO2_0 &= ~0x07; LPC_IOCON->PIO2_0 |= 0x01; /* UART_DTR as direction contronl */ LPC_UART->RS485CTRL |= (RS485_DCTRL|RS485_SEL); #endif #endif /* Enable the UART Interrupt */ NVIC_EnableIRQ(UART_IRQn); LPC_UART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */ return; }
/*********************************************************************//** * @brief Main SSP program body **********************************************************************/ int c_entry(void) { GPDMA_Channel_CFG_Type GPDMACfg; PINSEL_CFG_Type PinCfg; // DeInit NVIC and SCBNVIC NVIC_DeInit(); NVIC_SCBDeInit(); /* Configure the NVIC Preemption Priority Bits: * two (2) bits of preemption priority, six (6) bits of sub-priority. * Since the Number of Bits used for Priority Levels is five (5), so the * actual bit number of sub-priority is three (3) */ NVIC_SetPriorityGrouping(0x05); // Set Vector table offset value #if (__RAM_MODE__==1) NVIC_SetVTOR(0x10000000); #else NVIC_SetVTOR(0x00000000); #endif /* * Initialize SPI pin connect * P0.15 - SCK; * P0.16 - SSEL * P0.17 - MISO * P0.18 - MOSI */ PinCfg.Funcnum = 2; PinCfg.OpenDrain = 0; PinCfg.Pinmode = 0; PinCfg.Portnum = 0; PinCfg.Pinnum = 15; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 17; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 18; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 16; PINSEL_ConfigPin(&PinCfg); /* * Initialize debug via UART */ debug_frmwrk_init(); // print welcome screen print_menu(); /* Initializing SSP device section ------------------------------------------------------ */ // initialize SSP configuration structure to default SSP_ConfigStructInit(&SSP_ConfigStruct); // Initialize SSP peripheral with parameter given in structure above SSP_Init(LPC_SSP0, &SSP_ConfigStruct); // Enable SSP peripheral SSP_Cmd(LPC_SSP0, ENABLE); /* GPDMA Interrupt configuration section ------------------------------------------------- */ /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority(DMA_IRQn, ((0x01<<3)|0x01)); /* Enable SSP0 interrupt */ NVIC_EnableIRQ(DMA_IRQn); /* Initializing Buffer section ----------------------------------------------------------- */ Buffer_Init(); /* Initialize GPDMA controller */ GPDMA_Init(); /* Setting GPDMA interrupt */ // Disable interrupt for DMA NVIC_DisableIRQ (DMA_IRQn); /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority(DMA_IRQn, ((0x01<<3)|0x01)); /* Configure GPDMA channel 0 -------------------------------------------------------------*/ /* DMA Channel 0 */ GPDMACfg.ChannelNum = 0; // Source memory GPDMACfg.SrcMemAddr = (uint32_t) &dma_src; // Destination memory - Not used GPDMACfg.DstMemAddr = 0; // Transfer size GPDMACfg.TransferSize = sizeof(dma_src); // Transfer width - not used GPDMACfg.TransferWidth = 0; // Transfer type GPDMACfg.TransferType = GPDMA_TRANSFERTYPE_M2P; // Source connection - unused GPDMACfg.SrcConn = 0; // Destination connection GPDMACfg.DstConn = GPDMA_CONN_SSP0_Tx; // Linker List Item - unused GPDMACfg.DMALLI = 0; // Setup channel with given parameter GPDMA_Setup(&GPDMACfg, GPDMA_Callback0); /* Reset terminal counter */ Channel0_TC = 0; /* Reset Error counter */ Channel0_Err = 0; /* Configure GPDMA channel 1 -------------------------------------------------------------*/ /* DMA Channel 1 */ GPDMACfg.ChannelNum = 1; // Source memory - not used GPDMACfg.SrcMemAddr = 0; // Destination memory - Not used GPDMACfg.DstMemAddr = (uint32_t) &dma_dst; // Transfer size GPDMACfg.TransferSize = sizeof(dma_dst); // Transfer width - not used GPDMACfg.TransferWidth = 0; // Transfer type GPDMACfg.TransferType = GPDMA_TRANSFERTYPE_P2M; // Source connection GPDMACfg.SrcConn = GPDMA_CONN_SSP0_Rx; // Destination connection - not used GPDMACfg.DstConn = 0; // Linker List Item - unused GPDMACfg.DMALLI = 0; // Setup channel with given parameter GPDMA_Setup(&GPDMACfg, GPDMA_Callback1); /* Reset terminal counter */ Channel1_TC = 0; /* Reset Error counter */ Channel1_Err = 0; _DBG_("Start transfer..."); // Enable Tx and Rx DMA on SSP0 SSP_DMACmd (LPC_SSP0, SSP_DMA_RX, ENABLE); SSP_DMACmd (LPC_SSP0, SSP_DMA_TX, ENABLE); // Enable GPDMA channel 0 GPDMA_ChannelCmd(0, ENABLE); // Enable GPDMA channel 0 GPDMA_ChannelCmd(1, ENABLE); // Enable interrupt for DMA NVIC_EnableIRQ (DMA_IRQn); /* Wait for GPDMA processing complete */ while (((Channel0_TC == 0) && (Channel0_Err == 0)) \ || ((Channel1_TC == 0) && (Channel1_Err ==0))); /* Verify buffer */ Buffer_Verify(); _DBG_("Verify complete!"); /* Loop forever */ while(1); return 1; }
/************************************************************* Function: void UartInit(uint8_t num,uint32_t baudrate,uint8_t parity) Description: 串口初始化函数用于初始化RS232及RS485 将UART配置为中断接收,DMA发送,RS485自动切换方向 Calls: Called By: main() Input: num 串口号0、1、2 baudrate 波特率 parity 校验方式 Output: 无 Return: 无 Others: 无 *************************************************************/ void UartInit ( uint8_t num, uint32_t baudrate, uint8_t parity ) { // uint32_t idx; // RS485 configuration UART1_RS485_CTRLCFG_Type rs485cfg; // UART Configuration structure variable UART_CFG_Type UARTConfigStruct; // UART FIFO configuration Struct variable UART_FIFO_CFG_Type UARTFIFOConfigStruct; GPDMA_Channel_CFG_Type GPDMACfg; UART_ConfigStructInit ( &UARTConfigStruct ); UARTConfigStruct.Baud_rate = baudrate; UARTConfigStruct.Parity = parity; UART_FIFOConfigStructInit ( &UARTFIFOConfigStruct ); // Enable DMA mode in UART UARTFIFOConfigStruct.FIFO_DMAMode = ENABLE; // Destination memory - don't care GPDMACfgTx.DstMemAddr = 0; // Transfer width - don't care GPDMACfgTx.TransferWidth = 0; // Transfer type GPDMACfgTx.TransferType = GPDMA_TRANSFERTYPE_M2P; // Source connection - don't care GPDMACfgTx.SrcConn = 0; // Linker List Item - unused GPDMACfgTx.DMALLI = 0; rs485cfg.AutoDirCtrl_State = ENABLE; rs485cfg.DirCtrlPol_Level = SET; rs485cfg.DelayValue = 50; rs485cfg.NormalMultiDropMode_State = ENABLE; rs485cfg.AutoAddrDetect_State = DISABLE; rs485cfg.Rx_State = ENABLE; if ( num == 0 ) { //PINSEL_ConfigPin(0,2,1); //UART0 //PINSEL_ConfigPin(0,3,1); //UART0 PINSEL_ConfigPin ( 0, 25, 0x03 ); PINSEL_ConfigPin ( 0, 26, 0xb3 ); // Initalize UART0 peripheral with given to corresponding parameter UART_Init ( RS232_UART, &UARTConfigStruct ); // Initialize FIFO for UART0 peripheral UART_FIFOConfig ( RS232_UART, &UARTFIFOConfigStruct ); // Enable UART Transmit UART_TxCmd ( RS232_UART, ENABLE ); // channel 0 GPDMACfgTx.ChannelNum = 0; // Source memory GPDMACfgTx.SrcMemAddr = ( uint32_t ) &RS232Tx.Buff; // Transfer size GPDMACfgTx.TransferSize = sizeof ( RS232Tx.Buff ); // Destination connection GPDMACfgTx.DstConn = RS232_TX_PIN; RS232Tx.Flag = 0; RS232_Err = 0; UART_IntConfig ( RS232_UART, UART_INTCFG_RBR, ENABLE ); UART_IntConfig ( RS232_UART, UART_INTCFG_RLS, ENABLE ); NVIC_SetPriority ( RS232_IRQN, ( ( 0x01 << 3 ) | 0x01 ) ); NVIC_EnableIRQ ( RS232_IRQN ); RS232Rx.Flag = 0 ; RS232Rx.Len = 0 ; RS232Rx.Idx = 0 ; } if ( num == 1 ) { PINSEL_ConfigPin ( 2, 0, 2 ); PINSEL_ConfigPin ( 2, 1, 2 ); PINSEL_ConfigPin ( 2, 5, 2 ); //U1_DTR rs485cfg.DirCtrlPin = UART1_RS485_DIRCTRL_DTR; UART_Init ( ( LPC_UART_TypeDef * ) LPC_UART1, &UARTConfigStruct ); UART_FIFOConfig ( ( LPC_UART_TypeDef * ) LPC_UART1, &UARTFIFOConfigStruct ); UART_RS485Config ( ( LPC_UART_TypeDef * ) LPC_UART1, &rs485cfg ); // Enable UART Transmit UART_TxCmd ( ( LPC_UART_TypeDef * ) LPC_UART1, ENABLE ); GPDMACfgTx.ChannelNum = 1; // Source memory GPDMACfgTx.SrcMemAddr = ( uint32_t ) &RS485Tx1.Buff; // Transfer size GPDMACfgTx.TransferSize = sizeof ( RS485Tx1.Buff ); // Destination connection GPDMACfgTx.DstConn = GPDMA_CONN_UART1_Tx; /* Reset terminal counter */ RS485Tx1.Flag = 0; /* Reset Error counter */ RS4851_Err = 0; /* Enable UART Rx interrupt */ UART_IntConfig ( ( LPC_UART_TypeDef * ) LPC_UART1, UART_INTCFG_RBR, ENABLE ); /* Enable UART line status interrupt */ UART_IntConfig ( ( LPC_UART_TypeDef * ) LPC_UART1, UART_INTCFG_RLS, ENABLE ); /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority ( UART1_IRQn, ( ( 0x01 << 3 ) | 0x01 ) ); /* Enable Interrupt for UART0 channel */ NVIC_EnableIRQ ( UART1_IRQn ); } if ( num == 2 ) { PINSEL_ConfigPin ( 2, 8, 2 ); PINSEL_ConfigPin ( 2, 9, 2 ); PINSEL_ConfigPin ( 2, 6, 4 ); //U2_OE UART_Init ( LPC_UART2, &UARTConfigStruct ); UART_FIFOConfig ( LPC_UART2, &UARTFIFOConfigStruct ); UART_RS485Config ( ( LPC_UART_TypeDef * ) LPC_UART2, &rs485cfg ); // Enable UART Transmit UART_TxCmd ( LPC_UART2, ENABLE ); GPDMACfgTx.ChannelNum = 2; // Source memory GPDMACfgTx.SrcMemAddr = ( uint32_t ) &RS485Tx2.Buff; // Transfer size GPDMACfgTx.TransferSize = sizeof ( RS485Tx2.Buff ); // Destination connection GPDMACfgTx.DstConn = GPDMA_CONN_UART2_Tx; /* Reset terminal counter */ RS485Tx2.Flag = 0; /* Reset Error counter */ RS4852_Err = 0; /* Enable UART Rx interrupt */ UART_IntConfig ( LPC_UART2, UART_INTCFG_RBR, ENABLE ); /* Enable UART line status interrupt */ UART_IntConfig ( LPC_UART2, UART_INTCFG_RLS, ENABLE ); /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority ( UART2_IRQn, ( ( 0x01 << 3 ) | 0x01 ) ); /* Enable Interrupt for UART0 channel */ NVIC_EnableIRQ ( UART2_IRQn ); } /* Initialize GPDMA controller */ GPDMA_Init(); /* Setting GPDMA interrupt */ // Disable interrupt for DMA NVIC_DisableIRQ ( DMA_IRQn ); /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority ( DMA_IRQn, ( ( 0x01 << 3 ) | 0x01 ) ); // Setup channel with given parameter GPDMA_Setup ( &GPDMACfgTx ); // Enable interrupt for DMA NVIC_EnableIRQ ( DMA_IRQn ); // Enable GPDMA channel 0 //GPDMA_ChannelCmd(0, ENABLE); CRC_Init ( CRC_POLY_CRC16 ); }
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; switch (obj_s->uart) { #if defined(USART1_BASE) case UART_1: irq_n = USART1_IRQn; vector = (uint32_t)&uart1_irq; break; #endif #if defined(USART2_BASE) case UART_2: irq_n = USART2_IRQn; vector = (uint32_t)&uart2_irq; break; #endif #if defined(USART3_BASE) case UART_3: irq_n = USART3_IRQn; vector = (uint32_t)&uart3_irq; break; #endif #if defined(UART4_BASE) case UART_4: irq_n = UART4_IRQn; vector = (uint32_t)&uart4_irq; break; #endif #if defined(UART5_BASE) case UART_5: irq_n = UART5_IRQn; vector = (uint32_t)&uart5_irq; break; #endif #if defined(USART6_BASE) case UART_6: irq_n = USART6_IRQn; vector = (uint32_t)&uart6_irq; break; #endif #if defined(UART7_BASE) case UART_7: irq_n = UART7_IRQn; vector = (uint32_t)&uart7_irq; break; #endif #if defined(UART8_BASE) case UART_8: irq_n = UART8_IRQn; vector = (uint32_t)&uart8_irq; break; #endif #if defined(UART9_BASE) case UART_9: irq_n = UART9_IRQn; vector = (uint32_t)&uart9_irq; break; #endif #if defined(UART10_BASE) case UART_10: irq_n = UART10_IRQn; vector = (uint32_t)&uart10_irq; break; #endif } if (enable) { if (irq == RxIrq) { __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); } else { // TxIrq __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); } NVIC_SetVector(irq_n, vector); NVIC_EnableIRQ(irq_n); } else { // disable int all_disabled = 0; if (irq == RxIrq) { __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); // Check if TxIrq is disabled too if ((huart->Instance->CR1 & USART_CR1_TXEIE) == 0) { all_disabled = 1; } } else { // TxIrq __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); // Check if RxIrq is disabled too if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) { all_disabled = 1; } } if (all_disabled) { NVIC_DisableIRQ(irq_n); } } }
void DACClass::begin(uint32_t period) { // Enable clock for DAC pmc_enable_periph_clk(dacId); dacc_reset(dac); // Set transfer mode to double word dacc_set_transfer_mode(dac, 1); // Power save: // sleep mode - 0 (disabled) // fast wakeup - 0 (disabled) dacc_set_power_save(dac, 0, 0); // DAC refresh/startup timings: // refresh - 0x08 (1024*8 dacc clocks) // max speed mode - 0 (disabled) // startup time - 0x10 (1024 dacc clocks) dacc_set_timing(dac, 0x08, 0, DACC_MR_STARTUP_1024); // Flexible channel selection with tags dacc_enable_flexible_selection(dac); // Set up analog current dacc_set_analog_control(dac, DACC_ACR_IBCTLCH0(0x02) | DACC_ACR_IBCTLCH1(0x02) | DACC_ACR_IBCTLDACCORE(0x01)); // Enable output channels dacc_enable_channel(dac, 0); dacc_enable_channel(dac, 1); // Configure Timer Counter to trigger DAC // -------------------------------------- pmc_enable_periph_clk(ID_TC1); TC_Configure(TC0, 1, TC_CMR_TCCLKS_TIMER_CLOCK2 | // Clock at MCR/8 TC_CMR_WAVE | // Waveform mode TC_CMR_WAVSEL_UP_RC | // Counter running up and reset when equals to RC TC_CMR_ACPA_SET | TC_CMR_ACPC_CLEAR); const uint32_t TC = period / 8; TC_SetRA(TC0, 1, TC / 2); TC_SetRC(TC0, 1, TC); TC_Start(TC0, 1); // Configure clock source for DAC (2 = TC0 Output Chan. 1) dacc_set_trigger(dac, 2); // Configure pins PIO_Configure(g_APinDescription[DAC0].pPort, g_APinDescription[DAC0].ulPinType, g_APinDescription[DAC0].ulPin, g_APinDescription[DAC0].ulPinConfiguration); PIO_Configure(g_APinDescription[DAC1].pPort, g_APinDescription[DAC1].ulPinType, g_APinDescription[DAC1].ulPin, g_APinDescription[DAC1].ulPinConfiguration); // Enable interrupt controller for DAC dacc_disable_interrupt(dac, 0xFFFFFFFF); NVIC_DisableIRQ(isrId); NVIC_ClearPendingIRQ(isrId); NVIC_SetPriority(isrId, 0); NVIC_EnableIRQ(isrId); }
/** \fn int32_t PowerControl (ARM_POWER_STATE state) \brief Control Memory Card Interface Power. \param[in] state Power state \ref ARM_POWER_STATE \return \ref execution_status */ static int32_t PowerControl (ARM_POWER_STATE state) { switch (state) { case ARM_POWER_OFF: /* Disable SDIO interrupts */ NVIC_DisableIRQ(SDIO_IRQn); MCI.flags = MCI_INIT; /* Clear status */ MCI.status.command_active = 0U; MCI.status.command_timeout = 0U; MCI.status.command_error = 0U; MCI.status.transfer_active = 0U; MCI.status.transfer_timeout = 0U; MCI.status.transfer_error = 0U; MCI.status.sdio_interrupt = 0U; MCI.status.ccs = 0U; /* Reset peripheral */ LPC_RGU->RESET_CTRL0 = RGU_RESET_CTRL0_SDIO_RST; __NOP(); /* Disable SDIO interface clock */ LPC_CCU2->CLK_SDIO_CFG = 0; LPC_CCU1->CLK_M3_SDIO_CFG = 0; break; case ARM_POWER_FULL: if (!(MCI.flags & MCI_POWER)) { /* Clear response and transfer variables */ MCI.response = NULL; MCI.xfer.cnt = NULL; /* Enable SDIO clocks */ LPC_CCU1->CLK_M3_SDIO_CFG |= CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN; while (!(LPC_CCU1->CLK_M3_SDIO_CFG & CCU_CLK_STAT_RUN)); LPC_CCU2->CLK_SDIO_CFG |= CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN; while (!(LPC_CCU2->CLK_SDIO_CFG & CCU_CLK_STAT_RUN)); /* Reset controller, FIFO and DMA and wait until reset done */ LPC_SDMMC->CTRL = SDMMC_CTRL_RESET_BITMASK; while (LPC_SDMMC->CTRL & SDMMC_CTRL_RESET_BITMASK); LPC_SDMMC->BMOD = SDMMC_BMOD_SWR; while (LPC_SDMMC->BMOD & SDMMC_BMOD_SWR); /* Enable internal DMAC interrupts */ LPC_SDMMC->IDINTEN = SDMMC_IDINTEN_FBE | SDMMC_IDINTEN_DU ; /* Enable SD/MMC peripheral interrupts */ LPC_SDMMC->INTMASK = SDMMC_INTMASK_RE | #if (RTE_SD_CD_PIN_EN) SDMMC_INTMASK_CDET | #endif SDMMC_INTMASK_CDONE | SDMMC_INTMASK_DTO | SDMMC_INTMASK_RCRC | SDMMC_INTMASK_DCRC | SDMMC_INTMASK_RTO | SDMMC_INTMASK_DRTO | SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE ; /* Enable Global Interrupt and select internal DMA for data transfer */ LPC_SDMMC->CTRL = SDMMC_CTRL_INT_ENABLE | SDMMC_CTRL_USE_INTERNAL_DMAC; /* Set FIFO Threshold watermark */ LPC_SDMMC->FIFOTH = SDMMC_FIFOTH_DMA_MTS(0) | SDMMC_FIFOTH_RX_WMARK(14) | SDMMC_FIFOTH_TX_WMARK(15) ; /* Set Bus Mode */ LPC_SDMMC->BMOD = SDMMC_BMOD_DE; /* Set descriptor address */ LPC_SDMMC->DBADDR = (uint32_t)&SDMMC_DMA_Descriptor; /* Enable SDMMC peripheral interrupts in NVIC */ NVIC_ClearPendingIRQ(SDIO_IRQn); NVIC_EnableIRQ(SDIO_IRQn); MCI.flags |= MCI_POWER; } break; default: return ARM_DRIVER_ERROR_UNSUPPORTED; } return ARM_DRIVER_OK; }
void DACClass::end() { TC_Stop(TC0, 1); NVIC_DisableIRQ(isrId); dacc_disable_channel(dac, 0); dacc_disable_channel(dac, 1); }
void gpio_irq_disable(gpio_irq_t *obj) { NVIC_DisableIRQ(GPIO_IRQn); }
/** * \brief Disable re200b pir sensor */ void re200b_motion_detect_disable(void) { NVIC_DisableIRQ(ACC_IRQn); acc_disable_interrupt(ACC); acc_disable(ACC); }