int up_prioritize_irq(int irq, int priority) { uint32_t regaddr; uint32_t regval; int shift; DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) */ regaddr = NVIC_SYSH_PRIORITY(irq); irq -= 4; } else { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } regval = getreg32(regaddr); shift = ((irq & 3) << 3); regval &= ~(0xff << shift); regval |= (priority << shift); putreg32(regval, regaddr); stm32_dumpnvic("prioritize", irq); return OK; }
int up_prioritize_irq(int irq, int priority) { uint32_t regaddr; uint32_t regval; int shift; DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); if (irq < STM32_IRQ_INTERRUPTS) { irq -= 4; regaddr = NVIC_SYSH_PRIORITY(irq); } else { irq -= STM32_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } regval = getreg32(regaddr); shift = ((irq & 3) << 3); regval &= ~(0xff << shift); regval |= (priority << shift); putreg32(regval, regaddr); stm32_dumpnvic("prioritize", irq); return OK; }
int up_prioritize_irq(int irq, int priority) { uint32_t regaddr; uint32_t regval; int shift; DEBUGASSERT(irq >= EFM32_IRQ_MEMFAULT && irq < NR_VECTORS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); if (irq < EFM32_IRQ_INTERRUPTS) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) */ regaddr = NVIC_SYSH_PRIORITY(irq); irq -= 4; } else (irq < NR_VECTORS) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ irq -= EFM32_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); }
int up_prioritize_irq(int irq, int priority) { uint32_t regaddr; uint32_t regval; int shift; #ifdef CONFIG_ARMV7M_USEBASEPRI DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && priority >= NVIC_SYSH_DISABLE_PRIORITY && priority <= NVIC_SYSH_PRIORITY_MIN); #else DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); #endif if (irq < STM32_IRQ_INTERRUPTS) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) */ regaddr = NVIC_SYSH_PRIORITY(irq); irq -= 4; } else { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ irq -= STM32_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } regval = getreg32(regaddr); shift = ((irq & 3) << 3); regval &= ~(0xff << shift); regval |= (priority << shift); putreg32(regval, regaddr); stm32_dumpnvic("prioritize", irq); return OK; }