Bool NVAccelInitNV40TCL(ScrnInfoPtr pScrn) { NVPtr pNv = NVPTR(pScrn); struct nouveau_pushbuf *push = pNv->pushbuf; struct nv04_fifo *fifo = pNv->channel->data; uint32_t class = 0, chipset; int i; NVXVComputeBicubicFilter(pNv->scratch, XV_TABLE, XV_TABLE_SIZE); chipset = pNv->dev->chipset; if ((chipset & 0xf0) == NV_ARCH_40) { chipset &= 0xf; if (NV30_3D_CHIPSET_4X_MASK & (1<<chipset)) class = NV40_3D_CLASS; else if (NV44TCL_CHIPSET_4X_MASK & (1<<chipset))
Bool NVAccelInitNV30TCL(ScrnInfoPtr pScrn) { NVPtr pNv = NVPTR(pScrn); struct nouveau_pushbuf *push = pNv->pushbuf; struct nv04_fifo *fifo = pNv->channel->data; uint32_t class = 0, chipset; int i; NVXVComputeBicubicFilter(pNv->scratch, XV_TABLE, XV_TABLE_SIZE); #define NV30TCL_CHIPSET_3X_MASK 0x00000003 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0 #define NV30_3D_CHIPSET_3X_MASK 0x00000010 chipset = pNv->dev->chipset; if ((chipset & 0xf0) != NV_ARCH_30) return TRUE; chipset &= 0xf; if (NV30TCL_CHIPSET_3X_MASK & (1<<chipset)) class = NV30_3D_CLASS; else if (NV35TCL_CHIPSET_3X_MASK & (1<<chipset))