コード例 #1
0
ファイル: t30_uart.c プロジェクト: sncn-private/u-boot-t30
static void aos_CpuStallUsT30(NvU32 MicroSec)
{
    NvU32 Reg;
    NvU32 Delay;
    NvU32 MaxUs;

    // Get the maxium delay per loop.
    MaxUs = NV_DRF_NUM(FLOW_CTLR, HALT_CPU_EVENTS, ZERO, 0xFFFFFFFF);
    MicroSec += 1;

    while (MicroSec)
    {
        Delay   = (MicroSec > MaxUs) ? MaxUs : MicroSec;
        NV_ASSERT(Delay != 0);
        NV_ASSERT(Delay <= MicroSec);
        MicroSec -= Delay;

        Reg = NV_DRF_NUM(FLOW_CTLR, HALT_CPU_EVENTS, ZERO, Delay)
         | NV_DRF_NUM(FLOW_CTLR, HALT_CPU_EVENTS, uSEC, 1)
         | NV_DRF_DEF(FLOW_CTLR, HALT_CPU_EVENTS, MODE, FLOW_MODE_WAITEVENT);
        NV_FLOW_REGW(FLOW_PA_BASE, HALT_CPU_EVENTS, Reg);
        do
        {
             Reg = NV_FLOW_REGR(FLOW_PA_BASE, HALT_CPU_EVENTS);
             Reg = NV_DRF_VAL(FLOW_CTLR, HALT_CPU_EVENTS, ZERO, Reg);
        }while (Reg);
    }
}
コード例 #2
0
ファイル: ap15rm_memctrl.c プロジェクト: 0x0f/adam-kernel
static void Ap15CorePerfMonStart(NvU32* pEventList, NvU32* pEventListSize)
{
    NvU32 RegValue, Event0, Event1;

    // Just return maximum monitored events if no input list, otherwise
    // get both events ready (set the same if only one specified)
    if (*pEventListSize == 0)
    {
        *pEventListSize = NVRM_AP15_MONITORED_EVENTS_MAX;
        return;
    }
    Event0 = Event1 = pEventList[0];
    if (*pEventListSize >= NVRM_AP15_MONITORED_EVENTS_MAX)
    {
        Event1 = pEventList[1];
        *pEventListSize = NVRM_AP15_MONITORED_EVENTS_MAX;
    }

    // Reset, clear overflow flags and enable 3 performance counters:
    // total cycle counter and 2 event counters
    RegValue =
        NV_DRF_NUM(AP15_CP15, PMNC, ENABLE, 1) |
        NV_DRF_NUM(AP15_CP15, PMNC, EVENT_CNTS_RESET, 1) |
        NV_DRF_NUM(AP15_CP15, PMNC, CYCLE_CNT_RESET, 1) |
        NV_DRF_NUM(AP15_CP15, PMNC, CYCLE_CNT_OV, 1) |
        NV_DRF_NUM(AP15_CP15, PMNC, EVENT0_CNT_OV, 1) |
        NV_DRF_NUM(AP15_CP15, PMNC, EVENT1_CNT_OV, 1) |
        NV_DRF_NUM(AP15_CP15, PMNC, EVENT0, Event0) |
        NV_DRF_NUM(AP15_CP15, PMNC, EVENT1, Event1);
    MCR(p15, 0, RegValue, c15, c12, 0);
}
コード例 #3
0
ファイル: t30_uart.c プロジェクト: sncn-private/u-boot-t30
static NvError aos_UartSetBaudRateT30(NvU32 portNumber, NvU32 baud_rate)
{
    NvU32   BaudRateDivisor;
    NvU32   LineControlReg;
    volatile void* pUartRegs = 0;
    pUartRegs = (void*)s_UartBaseAddress[portNumber];
    // Compute the baudrate divisor
    // Prepare the divisor value.

#if 0 // jz
    if (GetMajorVersion() == 0)
        BaudRateDivisor = (13000 * 1000) / (baud_rate *16); //for emulation
    else
#endif
        BaudRateDivisor = (AOS_PLLP_FIXED_FREQ_KHZ * 1000) / (baud_rate *16);

    // Set the divisor latch bit to allow access to divisor registers (DLL/DLM)
    LineControlReg = NV_UART_REGR(pUartRegs, LCR);
    LineControlReg |= NV_DRF_NUM(UART, LCR, DLAB, 1);
    NV_UART_REGW(pUartRegs, LCR, LineControlReg);

    // First write the LSB of the baud rate divisor
    NV_UART_REGW(pUartRegs, THR_DLAB_0, BaudRateDivisor & 0xFF);

    // Now write the MSB of the baud rate divisor
    NV_UART_REGW(pUartRegs, IER_DLAB_0, (BaudRateDivisor >> 8) & 0xFF);

    // Now that the baud rate has been set turn off divisor latch
    // bit to allow access to receive/transmit holding registers
    // and interrupt enable register.
    LineControlReg &= ~NV_DRF_NUM(UART, LCR, DLAB, 1);
    NV_UART_REGW(pUartRegs, LCR, LineControlReg);

    return NvError_Success;
}
コード例 #4
0
void
NvRmPrivAp20EmcMonitorsStart(
    const NvRmDfs* pDfs,
    const NvRmDfsFrequencies* pDfsKHz,
    const NvU32 IntervalMs)
{
    NvU32 RegValue, SavedRegValue;
    void* pEmcRegs = pDfs->Modules[NvRmDfsModuleId_Emc].pBaseReg;

    // EMC sample period is specified in EMC clock cycles, accuracy 0-16 cycles.
    #define MEAN_EMC_LIMIT_ERROR (8)
    NvU32 cycles = IntervalMs * pDfsKHz->Domains[NvRmDfsClockId_Emc] +
                    MEAN_EMC_LIMIT_ERROR;
    /*
     * Start EMC power monitor for the next sample period: clear EMC counters,
     * set sample interval limit in EMC cycles, enable monitoring. Monitor is
     * counting EMC 1x clock cycles while any memory access is detected. 
     */
    SavedRegValue = NV_EMC_REGR(pEmcRegs, STAT_CONTROL);
    RegValue = NV_FLD_SET_DRF_DEF(EMC, STAT_CONTROL, PWR_GATHER, CLEAR, SavedRegValue);
    NV_EMC_REGW(pEmcRegs, STAT_CONTROL, RegValue);

    RegValue = NV_DRF_NUM(EMC, STAT_PWR_CLOCK_LIMIT, PWR_CLOCK_LIMIT, cycles);
    NV_EMC_REGW(pEmcRegs, STAT_PWR_CLOCK_LIMIT, RegValue);

    RegValue = NV_FLD_SET_DRF_DEF(EMC, STAT_CONTROL, PWR_GATHER, ENABLE, SavedRegValue);
    NV_EMC_REGW(pEmcRegs, STAT_CONTROL, RegValue);
}
コード例 #5
0
ファイル: ap15rm_memctrl.c プロジェクト: 0x0f/adam-kernel
NvError
ReadObsData(
        NvRmDeviceHandle rm,
        NvRmModuleID modID,
        NvU32 start_index,
        NvU32 length,
        NvU32 *value)
{
    NvU32 i = 0, offset = 0, value1, value2;
    NvU32 timeout;
    NvU32 partID = 0xffffffff;
    NvU32 index, temp;

    for (i = 0; i < ObsInfoTableSize; i++)
    {
        if (modID == ObsInfoTable[i].modSelect)
        {
        partID = ObsInfoTable[i].partSelect;
        break;
        }
    }
    if (i == ObsInfoTableSize)
    {
        return NvError_BadParameter;
    }

    for(offset = 0; offset < length; offset++)
    {
        index = start_index + offset;
        temp = NV_DRF_DEF(APB_MISC_GP, OBSCTRL, OBS_EN, ENABLE) |
            NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_MOD_SEL, modID) |
            NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_PART_SEL, partID) |
            NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_SIG_SEL, index) ;
        NV_REGW(rm, NvRmModuleID_Misc, 0, APB_MISC_GP_OBSCTRL_0, temp);
        value1 = NV_REGR(rm, NvRmModuleID_Misc, 0, APB_MISC_GP_OBSCTRL_0);
        timeout = 100;
        do {
            value2 = value1;
            value1 = NV_REGR(rm, NvRmModuleID_Misc, 0, APB_MISC_GP_OBSDATA_0);
            timeout --;
        } while (value1 != value2 && timeout);
        NvOsDebugPrintf("OBS bus modID 0x%x index 0x%x = value 0x%x",
                modID, index, value1);
        value[offset] = value1;
    }
    return NvSuccess;
}
コード例 #6
0
ファイル: t30_uart.c プロジェクト: sncn-private/u-boot-t30
volatile void* aos_UartInitT30(NvU32 portNumber, NvU32 baud_rate)
{
    volatile void* pUart;
    NvU32   LineControlReg;
    NvU32   FifoControlReg;
    NvU32   ModemControlReg;
    pUart = (void*)s_UartBaseAddress[portNumber];
    aos_EnableUartT30(portNumber);
    aos_UartResetPortT30(portNumber);
    // Select the clock source for the UART.
    aos_SetUartClockSourceT30(portNumber);
    // Initialize line control register: no parity, 1 stop bit, 8 data bits.
    LineControlReg = NV_DRF_NUM(UART, LCR, PAR, 0)
         | NV_DRF_NUM(UART, LCR, STOP, 0)
         | NV_DRF_NUM(UART, LCR, WD_SIZE, 3);
    NV_UART_REGW(pUart, LCR, LineControlReg);

    // Setup baud rate
    if (aos_UartSetBaudRateT30(portNumber, baud_rate) != NvError_Success)
    {
        return 0;
    }
    // Clear and enable the transmit and receive FIFOs.
    FifoControlReg = NV_DRF_NUM(UART, IIR_FCR, TX_CLR, 1)
         | NV_DRF_NUM(UART, IIR_FCR, RX_CLR, 1)
         | NV_DRF_NUM(UART, IIR_FCR, FCR_EN_FIFO, 1);
    NV_UART_REGW(pUart, IIR_FCR, FifoControlReg);

    // Assert DTR (Data Terminal Ready) so that the other side knows we're ready.
    ModemControlReg  = NV_UART_REGR(pUart, MCR);
    ModemControlReg |= NV_DRF_NUM(UART, MCR, DTR, 1);
    NV_UART_REGW(pUart, MCR, ModemControlReg);
    return pUart;
}
コード例 #7
0
ファイル: t30_uart.c プロジェクト: sncn-private/u-boot-t30
static void aos_UartWriteByteT30(volatile void* pUart, NvU8 ch)
{
    NvU32 LineStatusReg;
    // Wait for transmit buffer to be empty.
    do
    {
        LineStatusReg = NV_UART_REGR(pUart, LSR);
    } while (!(LineStatusReg & NV_DRF_NUM(UART, LSR, THRE, 1)));
    // Write the character.
    NV_UART_REGW(pUart, THR_DLAB_0, ch);
}
コード例 #8
0
/**
 *  Power suspend for mouse.
 *
 */
NvBool NvOdmMousePowerSuspend(NvOdmMouseDeviceHandle hDevice)
{
#if ECI_MOUSE_DISABLE_SUPPORTED
    NvError e;
    NvEcRequest *pRequest = hDevice->pRequest;
    NvEcResponse *pResponse = hDevice->pResponse;
    NvU32 Index = 0;

    if (!hDevice || !pRequest || !pResponse)
        return NV_FALSE;

    NV_ASSERT(hDevice->hEc);
    NV_ASSERT(hDevice->pRequest);
    NV_ASSERT(hDevice->pResponse);

    // cancel auto-receive (disables event reporting)

    NVODM_PRINTF(("NvOdmMousePowerSuspend: Cancel Auto Receive\n"));

    do
    {
        // fill up request structure
        pRequest->PacketType = NvEcPacketType_Request;
        pRequest->RequestType = NvEcRequestResponseType_AuxDevice;
        pRequest->RequestSubtype = 
            ((NvEcRequestResponseSubtype) 
             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,hDevice->ValidMousePorts[Index]))) |
            ((NvEcRequestResponseSubtype) 
             NvEcAuxDeviceSubtype_CancelAutoReceive);
        pRequest->NumPayloadBytes = 0;

        // Request to EC
        e = NvEcSendRequest(hDevice->hEc, pRequest, pResponse, sizeof(*pRequest),
                        sizeof(*pResponse));
        
        if (NvSuccess != e)
        {
            NVODMMOUSE_PRINTF(("NvOdmMousePowerSuspend: NvEcSendRequest failed !!"));
            return NV_FALSE;
        }

        if (NvEcStatus_Success != pResponse->Status)
        {
            NVODMMOUSE_PRINTF(("NvOdmMousePowerSuspend: EC response failed !!"));
            return NV_FALSE;
        }
     } while(hDevice->ValidMousePorts[++Index] != INVALID_MOUSE_PORT_ID);
#endif
    NVODM_PRINTF(("NvOdmMousePowerSuspend: Exit success\n"));

    return NV_TRUE;
}
コード例 #9
0
NvBool
NvOdmMouseSendRequest(
    NvOdmMouseDeviceHandle hDevice, 
    NvU32 cmd, 
    NvU32 ExpectedResponseSize,
    NvU32 *NumPayLoad, 
    NvU8 *PayLoadBuf)
{
    NvError e;
    NvEcRequest *pRequest = hDevice->pRequest;
    NvEcResponse *pResponse = hDevice->pResponse;
    NvU32 Index = 0;

    do
    {
        // fill up request structure
        pRequest->PacketType = NvEcPacketType_Request;
        pRequest->RequestType = NvEcRequestResponseType_AuxDevice;
        pRequest->RequestSubtype = 
            ((NvEcRequestResponseSubtype) 
             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,hDevice->ValidMousePorts[Index]))) |
            ((NvEcRequestResponseSubtype) 
             NvEcAuxDeviceSubtype_SendCommand);
        pRequest->NumPayloadBytes = 2;
        pRequest->Payload[0] = cmd; // set the command
        pRequest->Payload[1] = ExpectedResponseSize;

        // Request to EC
        e = NvEcSendRequest(hDevice->hEc, pRequest, pResponse, sizeof(*pRequest),
                        sizeof(*pResponse));
        
        if (NvSuccess != e)
        {
            NVODMMOUSE_PRINTF(("NvEcSendRequest failed !!"));
            return NV_FALSE;
        }

        if (NvEcStatus_Success != pResponse->Status)
        {
            NVODMMOUSE_PRINTF(("EC response failed !!"));
            return NV_FALSE;
        }

        // store/process the Mouse response and return to the client driver
        *NumPayLoad = pResponse->NumPayloadBytes;
        NvOdmOsMemcpy(PayLoadBuf, &pResponse->Payload, *NumPayLoad);
    } while (hDevice->ValidMousePorts[++Index] != INVALID_MOUSE_PORT_ID);

    return NV_TRUE;
}
コード例 #10
0
ファイル: t30_uart.c プロジェクト: sncn-private/u-boot-t30
static NvU8 aos_UartReadByteT30(volatile void* pUart)
{
    NvU8 ch;
    NvU32 LineStatusReg;
    // Wait for some time to get the data
    do
    {
        LineStatusReg = NV_UART_REGR(pUart, LSR);
    } while (!(LineStatusReg & NV_DRF_NUM(UART, LSR, RDR, 1)));
//    } while (NV_DRF_VAL(UART, LSR, RDR, LineStatusReg) != UART_LSR_0_RDR_DATA_IN_FIFO);

    // Read the character.
//    ch = NV_UART_REGR(pUart, RBR);
    ch = NV_UART_REGR(pUart, THR_DLAB_0);
    return ch;
}
コード例 #11
0
ファイル: t30_uart.c プロジェクト: sncn-private/u-boot-t30
void t30_UartA_Init(void)
{
    NvU32 RegData;

    // Initialization is responsible for correct pin mux configuration
    // It also needs to wait for the correct osc frequency to be known
    // IMPORTANT, there is some unspecified logic in the UART that always 
    // operate off PLLP_out3, mail from Robert Quan says that correct operation
    // of UART without starting PLLP requires
    // - to put PLLP in bypass
    // - to override the PLLP_ou3 divider to be 1 (or put in bypass)
    // This is done like that here to avoid any dependence on PLLP analog circuitry 
    // operating correctly

    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_BASE_0);
    RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_BASE_0, RegData);
    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_OUTB_0);
    RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_OUTB,
        PLLP_OUT3_OVRRIDE, ENABLE);
    RegData |= NV_DRF_NUM(CLK_RST_CONTROLLER,
        PLLP_OUTB, PLLP_OUT3_RATIO, 0);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_OUTB_0, RegData);

    // Set up the pinmuxes to bring UARTA out on ULPI_DATA0 and ULPI_DATA1
    // for T30.  All alternate mappings of UARTA are set to select an input other than UARTA.
    //
    //     UART2_RTS_N => Alternate 3 ( SPI4 instead of UA3_TXD)
    //     UART2_CTS_N => Alternate 3 ( SPI4 instead of UA3_TXD)
    //     ULPI_DATA0  =>Alternate 2 (UA3_TXD)
    //     ULPI_DATA1  =>Alternate 2 UA3_RXD)
    //     SDMMC1_DAT3 => Primary     (SDMMC1_DAT3 instead of UA3_TXD)
    //     SDMMC1_DAT2 => Primary     (SDMMC1_DAT2 instead of UA3_RXD)
    //     GPIO_PU0    => Alternate 2 (GMI_A6 instead of UA3_TXD)
    //     GPIO_PU1    => Alternate 2 (GMI_A7 instead of UA3_RXD)
    //     SDMMC3_CLK  => Alternate 2 (SDMMC3_SCLK instead of UA3_TXD)
    //     SDMMC3_CMD  => Alternate 2 (SDMMC3_CMD instead of UA3_RXD)
    //
    // Last reviewed on 08/27/2010
    SET_PIN(UART2_RTS_N,PM,SPI4) ;
    SET_PIN(UART2_CTS_N,PM,SPI4) ;
    SET_PIN(ULPI_DATA0,PM,UARTA) ;
    SET_PIN(ULPI_DATA1,PM,UARTA) ;
    SET_PIN(SDMMC1_DAT3,PM,SDMMC1) ;
    SET_PIN(SDMMC1_DAT2,PM,SDMMC1) ;
    SET_PIN(GPIO_PU0,PM,GMI) ;
    SET_PIN(GPIO_PU1,PM,GMI) ;
    SET_PIN(SDMMC3_CLK,  PM, SDMMC3);
    SET_PIN(SDMMC3_CMD,  PM, SDMMC3);
    // Enable the pads.
    SET_PIN(ULPI_DATA0, TRISTATE, NORMAL);
    SET_PIN(ULPI_DATA1, TRISTATE, NORMAL);

    // enable UART A clock, toggle reset  
    RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0);
    RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_L, 
        CLK_ENB_UARTA, ENABLE);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
                       CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0, RegData);
    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_L_0);
    RegData  = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_L,
        SWR_UARTA_RST, ENABLE, RegData);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_L_0, RegData);
    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_L_0);
    RegData  = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_L,
        SWR_UARTA_RST, DISABLE, RegData);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_L_0, RegData);

    // Then there is the specific set up for UART itself, including the clock configuration.
    // configure at top for source & configure the divider, internal to uart for obscure reasons
    // when UARTA_DIV_ENB is enable DLL/DLLM programming is not required
    //.Refer to the CLK_SOURCE_UARTA reg description in arclk_rst
    // UARTA_DIV_ENB is disabled as new divisor logic is not enabled on FPGA Bug #739606 
    NV_WRITE32(NV_ADDRESS_MAP_CAR_BASE+
        CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0 ,
        (CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_CLK_M <<
        CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT) |
        (CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_DISABLE <<
        CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_SHIFT) |
        0);

}
コード例 #12
0
NvBool
NvOdmMouseDeviceOpen(
    NvOdmMouseDeviceHandle *hDevice)
{
    NvOdmMouseDevice *hMouseDev = NULL;
    NvBool ret = NV_FALSE;
    NvU32 InstanceId = 0, count = 0, MousePort = 0, i = 0;
#if WAKE_FROM_MOUSE
    NvError err = NvError_Success;
    NvEcRequest Request = {0};
    NvEcResponse Response = {0};
#endif

    // Allocate memory for request type structure
    hMouseDev = (NvOdmMouseDevice *)NvOdmOsAlloc(sizeof(NvOdmMouseDevice));
    if (!hMouseDev)
    {
        ret = NV_FALSE;
        NVODMMOUSE_PRINTF(("NvOdmOsAlloc failed to allocate hMouseDev!!"));
        goto fail_safe;
    }
    NvOdmOsMemset(hMouseDev, 0, sizeof(NvOdmMouseDevice));

    // open channel to the EC
    if ((NvEcOpen(&hMouseDev->hEc, InstanceId)) != NvSuccess)
    {
        ret = NV_FALSE;
        NVODMMOUSE_PRINTF(("NvEcOpen failed !!"));
        goto fail_safe;
    }

    hMouseDev->pRequest = NULL;
    hMouseDev->pResponse = NULL;
    hMouseDev->pEvent = NULL;
    hMouseDev->CompressionEnabled = NV_FALSE;
    hMouseDev->CompressionState = 0x0;

    do
    {
        hMouseDev->ValidMousePorts[count] = INVALID_MOUSE_PORT_ID;
        count++;
    } while (count <= MAX_NUM_MOUSE_PORTS);

    // Allocate memory for request type structure
    hMouseDev->pRequest = NvOdmOsAlloc(sizeof(NvEcRequest));
    if (!hMouseDev->pRequest)
    {
        ret = NV_FALSE;
        NVODMMOUSE_PRINTF(("NvOdmOsAlloc failed to allocate pRequest!!"));
        goto fail_safe;
    }
    NvOdmOsMemset(hMouseDev->pRequest, 0, sizeof(NvEcRequest));

    // Allocate memory for response type structure
    hMouseDev->pResponse = NvOdmOsAlloc(sizeof(NvEcResponse));
    if (!hMouseDev->pResponse)
    {
        ret = NV_FALSE;
        NVODMMOUSE_PRINTF(("NvOdmOsAlloc failed to allocate pResponse!!"));
        goto fail_safe;
    }
    NvOdmOsMemset(hMouseDev->pResponse, 0, sizeof(NvEcResponse));

    // Allocate memory for event type structure
    hMouseDev->pEvent = NvOdmOsAlloc(sizeof(NvEcEvent));
    if (!hMouseDev->pEvent)
    {
        ret = NV_FALSE;
        NVODMMOUSE_PRINTF(("NvOdmOsAlloc failed to allocate pEvent!!"));
        goto fail_safe;
    }
    NvOdmOsMemset(hMouseDev->pEvent, 0, sizeof(NvEcEvent));

    MousePort = MOUSE_PS2_PORT_ID_0;
    count = CMD_MAX_RETRIES + 1; i = 0;
    while (count--)
    {
        // fill up request structure
        Request.PacketType = NvEcPacketType_Request;
        Request.RequestType = NvEcRequestResponseType_AuxDevice;
        Request.RequestSubtype = 
            ((NvEcRequestResponseSubtype) 
             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,MousePort))) |
            ((NvEcRequestResponseSubtype) 
             NvEcAuxDeviceSubtype_SendCommand);
        Request.NumPayloadBytes = 2;
        Request.Payload[0] = 0xFF; // set the reset command
        Request.Payload[1] = 3;

        // Request to EC
        err = NvEcSendRequest(hMouseDev->hEc, &Request, &Response, sizeof(Request),
                        sizeof(Response));

        if (NvSuccess != err)
        {
            NVODMMOUSE_PRINTF(("NvEcSendRequest failed !!"));
            break;
        }

        // mouse not found
        if (NvEcStatus_Success != Response.Status)
        {
            NVODMMOUSE_PRINTF(("EC response failed !!"));
            if (MousePort != MOUSE_PS2_PORT_ID_1)
            {
                count = CMD_MAX_RETRIES + 1;
                MousePort = MOUSE_PS2_PORT_ID_1;
                continue;
            }
            break;
        }

        if (Response.NumPayloadBytes != 3)
            continue;

        // success
        if (Response.Payload[0] == 0xFA)
        {
            hMouseDev->ValidMousePorts[i] = MousePort;
            if (MousePort != MOUSE_PS2_PORT_ID_1)
            {
                count = CMD_MAX_RETRIES + 1;
                MousePort = MOUSE_PS2_PORT_ID_1;
                i++;
                continue;
            }
            break;
        }
    }

#if WAKE_FROM_MOUSE
    i = 0;
    do
    {
        /* enable mouse as wake up source */
        Request.PacketType = NvEcPacketType_Request;
        Request.RequestType = NvEcRequestResponseType_AuxDevice;
        Request.RequestSubtype = ((NvEcRequestResponseSubtype) 
             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,hMouseDev->ValidMousePorts[i]))) |
             (NvEcRequestResponseSubtype)
             NvEcAuxDeviceSubtype_ConfigureWake;
        Request.NumPayloadBytes = 2;
        Request.Payload[0] = NVEC_AUX_DEVICE_WAKE_ENABLE_0_ACTION_ENABLE;
        Request.Payload[1] = NVEC_AUX_DEVICE_EVENT_TYPE_0_ANY_EVENT_ENABLE;

        err = NvEcSendRequest(
                    hMouseDev->hEc,
                    &Request,
                    &Response,
                    sizeof(Request),
                    sizeof(Response));
        if (err != NvError_Success)
        {
            ret = NV_FALSE;
            goto fail_safe;
        }

        if (Response.Status != NvEcStatus_Success)
        {
            ret = NV_FALSE;
            goto fail_safe;
        }
    } while (hMouseDev->ValidMousePorts[++i] != INVALID_MOUSE_PORT_ID);
#endif

    *hDevice = (NvOdmMouseDeviceHandle)hMouseDev;
    ret = NV_TRUE;
    return ret;

fail_safe:
    NvOdmMouseDeviceClose((NvOdmMouseDeviceHandle)hMouseDev);
    hMouseDev = NULL;
    return ret;
}
コード例 #13
0
NvBool
NvOdmMouseStartStreaming(
    NvOdmMouseDeviceHandle hDevice,
    NvU32 NumBytesPerSample)
{
    NvError e;
    NvEcRequest *pRequest = hDevice->pRequest;
    NvEcResponse *pResponse = hDevice->pResponse;
    NvU32 Index = 0;

    if (!hDevice)
        return NV_FALSE;

    hDevice->NumBytesPerSample = NumBytesPerSample;

#if ENABLE_COMPRESSION
    /**
     * automatically enable compression if sample size is 3 bytes
     *
     * compression is supported only for 3-byte data packets (which is the
     * common case for ps/2 mice and mouses
     *
     * compression reduces communication bandwidth by eliminating the first data
     * byte of the packet when it hasn't changed relative to the previous
     * packet.  Whenever a full-sized packet is sent, the first payload byte is
     * latched so that it can be inserted into an n y following compressed packets.
     */

    if (NumBytesPerSample == 3)
    {
        do
        {
            // prepare Aux Device request for Set Compression
            pRequest->PacketType = NvEcPacketType_Request;
            pRequest->RequestType = NvEcRequestResponseType_AuxDevice;
            pRequest->RequestSubtype = 
                ((NvEcRequestResponseSubtype) 
                 (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,hDevice->ValidMousePorts[Index]))) |
                ((NvEcRequestResponseSubtype) 
                 NvEcAuxDeviceSubtype_SetCompression);
            pRequest->NumPayloadBytes = 1; 
            pRequest->Payload[0] = 1; // enable compression

            // send request to EC
            e = NvEcSendRequest(hDevice->hEc, pRequest, pResponse, sizeof(*pRequest),
                                sizeof(*pResponse));

            if (NvSuccess != e)
            {
                NVODMMOUSE_PRINTF(("NvEcSendRequest (compression) failed !!"));
                return NV_FALSE;
            }

            // check status reported by EC
            if (NvEcStatus_Success != pResponse->Status)
            {
                NVODMMOUSE_PRINTF(("EC response (compression) failed !!"));
                return NV_FALSE;
            }
        } while(hDevice->ValidMousePorts[++Index] != INVALID_MOUSE_PORT_ID);

        hDevice->CompressionEnabled = NV_TRUE;
        hDevice->CompressionState = 0x0;
    }
    else
    {
        // compression not supported due to packet size (!= 3 bytes)
        hDevice->CompressionEnabled = NV_FALSE;
    }
#else // ENABLE_COMPRESSION
    // disable compression
    hDevice->CompressionEnabled = NV_FALSE;
#endif // ENABLE_COMPRESSION

    // prepare Aux Device request for Auto-Receive N Bytes
    Index = 0;
    do
    {
        pRequest->PacketType = NvEcPacketType_Request;
        pRequest->RequestType = NvEcRequestResponseType_AuxDevice;
        pRequest->RequestSubtype = 
            ((NvEcRequestResponseSubtype) 
             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,hDevice->ValidMousePorts[Index]))) |
            ((NvEcRequestResponseSubtype) 
             NvEcAuxDeviceSubtype_AutoReceiveBytes);
        pRequest->NumPayloadBytes = 1; 
        pRequest->Payload[0] = NumBytesPerSample;

        // send request to EC
        e = NvEcSendRequest(hDevice->hEc, pRequest, pResponse, sizeof(*pRequest),
                        sizeof(*pResponse));

        if (NvSuccess != e)
        {
            NVODMMOUSE_PRINTF(("NvEcSendRequest (auto-receive) failed !!"));
            return NV_FALSE;
        }

        // check status reported by EC
        if (NvEcStatus_Success != pResponse->Status)
        {
            NVODMMOUSE_PRINTF(("EC response (auto-receive) failed !!"));
            return NV_FALSE;
        }
    } while(hDevice->ValidMousePorts[++Index] != INVALID_MOUSE_PORT_ID);

    return NV_TRUE;
}
コード例 #14
0
ファイル: ap15rm_memctrl.c プロジェクト: 0x0f/adam-kernel
static void Ap15CorePerfMonDisable(void)
{
    // Disable all performance counters
    NvU32 RegValue = NV_DRF_NUM(AP15_CP15, PMNC, ENABLE, 0);
    MCR(p15, 0, RegValue, c15, c12, 0);
}
コード例 #15
0
ファイル: t30_uart.c プロジェクト: sncn-private/u-boot-t30
void t30_UartC_Init(void)
{
    NvU32 RegData;

    // Initialization is responsible for correct pin mux configuration
    // It also needs to wait for the correct osc frequency to be known
    // IMPORTANT, there is some unspecified logic in the UART that always 
    // operate off PLLP_out3, mail from Robert Quan says that correct operation
    // of UART without starting PLLP requires
    // - to put PLLP in bypass
    // - to override the PLLP_ou3 divider to be 1 (or put in bypass)
    // This is done like that here to avoid any dependence on PLLP analog circuitry 
    // operating correctly

    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_BASE_0);
    RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_BASE_0, RegData);
    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_OUTB_0);
    RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_OUTB,
        PLLP_OUT3_OVRRIDE, ENABLE);
    RegData |= NV_DRF_NUM(CLK_RST_CONTROLLER,
        PLLP_OUTB, PLLP_OUT3_RATIO, 0);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_OUTB_0, RegData);

    // Set up the pinmuxes to bring UARTC out on uart3_txd and uart_rxd
    // for oregon T30.
    //
    //     UART3_TXD  =>primary 0 (UC3_TXD)
    //     UART3_RXD  =>primary 0(UC3_RXD)
    //
    SET_PIN(UART3_TXD,PM,UARTC) ;
    SET_PIN(UART3_RXD,PM,UARTC) ;
//    SET_PIN(UART3_CTS_N,PM,UARTC) ;
//    SET_PIN(UART3_RTS_N,PM,UARTC) ;

    // Enable the pads.
    SET_PIN(UART3_TXD, TRISTATE, NORMAL);
    SET_PIN(UART3_RXD, TRISTATE, NORMAL);

    // enable UART C clock, toggle reset  
    RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
    RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_H, 
        CLK_ENB_UARTC, ENABLE);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
                       CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, RegData);
    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_H_0);
    RegData  = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_H,
        SWR_UARTC_RST, ENABLE, RegData);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_H_0, RegData);
    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_H_0);
    RegData  = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_H,
        SWR_UARTC_RST, DISABLE, RegData);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_H_0, RegData);

    // Then there is the specific set up for UART itself, including the clock configuration.
    // configure at top for source & configure the divider, internal to uart for obscure reasons
    // when UARTC_DIV_ENB is enable DLL/DLLM programming is not required
    //.Refer to the CLK_SOURCE_UARTD reg description in arclk_rst
    // UARTD_DIV_ENB is disabled as new divisor logic is not enabled on FPGA Bug #739606 
#if 0
    NV_WRITE32(NV_ADDRESS_MAP_CAR_BASE+
        CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0 ,
        (CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_CLK_M <<
        CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT) |
        (CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_DISABLE <<
        CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SHIFT) |
        0);
#endif

}
コード例 #16
0
ファイル: t30_uart.c プロジェクト: sncn-private/u-boot-t30
void t30_UartD_Init(void)
{
    NvU32 RegData;

    // Initialization is responsible for correct pin mux configuration
    // It also needs to wait for the correct osc frequency to be known
    // IMPORTANT, there is some unspecified logic in the UART that always 
    // operate off PLLP_out3, mail from Robert Quan says that correct operation
    // of UART without starting PLLP requires
    // - to put PLLP in bypass
    // - to override the PLLP_ou3 divider to be 1 (or put in bypass)
    // This is done like that here to avoid any dependence on PLLP analog circuitry 
    // operating correctly

    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_BASE_0);
    RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_BASE_0, RegData);
    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_OUTB_0);
    RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_OUTB,
        PLLP_OUT3_OVRRIDE, ENABLE);
    RegData |= NV_DRF_NUM(CLK_RST_CONTROLLER,
        PLLP_OUTB, PLLP_OUT3_RATIO, 0);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_PLLP_OUTB_0, RegData);

    // Set up the pinmuxes to bring UARTD out on ULPI_clk and ULPI_dir
    // for waluigi T30.  All alternate mappings of UARTD are set to select an input other than UARTD.
    //
    //     GMI_AD16 => Alternate 1 ( SPI4 instead of UD3_TXD)
    //     GMI_AD17 => Alternate 1 ( SPI4 instead of UD3_RXD)
    //     ULPI_CLK  =>Alternate 2 (UD3_TXD)
    //     ULPI_DIR  =>Alternate 2 UD3_RXD)
    //
    // Last reviewed on 08/27/2010
    SET_PIN(GMI_A16,PM,SPI4) ;
    SET_PIN(GMI_A17,PM,SPI4) ;
    SET_PIN(ULPI_CLK,PM,UARTD) ;
    SET_PIN(ULPI_DIR,PM,UARTD) ;

    // Enable the pads.
    SET_PIN(ULPI_CLK, TRISTATE, NORMAL);
    SET_PIN(ULPI_DIR, TRISTATE, NORMAL);

    // enable UART D clock, toggle reset  
    RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0);
    RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_U, 
        CLK_ENB_UARTD, ENABLE);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
                       CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0, RegData);
    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_U_0);
    RegData  = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_U,
        SWR_UARTD_RST, ENABLE, RegData);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_U_0, RegData);
    RegData  = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_U_0);
    RegData  = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_U,
        SWR_UARTD_RST, DISABLE, RegData);
    NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
        CLK_RST_CONTROLLER_RST_DEVICES_U_0, RegData);

    // Then there is the specific set up for UART itself, including the clock configuration.
    // configure at top for source & configure the divider, internal to uart for obscure reasons
    // when UARTD_DIV_ENB is enable DLL/DLLM programming is not required
    //.Refer to the CLK_SOURCE_UARTD reg description in arclk_rst
    // UARTD_DIV_ENB is disabled as new divisor logic is not enabled on FPGA Bug #739606 
#if 0
    NV_WRITE32(NV_ADDRESS_MAP_CAR_BASE+
        CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0 ,
        (CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_CLK_M <<
        CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT) |
        (CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_DISABLE <<
        CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SHIFT) |
        0);
#endif

}
コード例 #17
0
NvBool
NvOdmMouseReset(NvOdmMouseDeviceHandle hDevice)
{
    NvError err = NvError_Success;
    NvEcRequest Request = {0};
    NvEcResponse Response = {0};
    NvU32 count = 0, MousePort = 0, i = 0;
    NvBool ret = NV_FALSE;
    NvOdmMouseDevice *hMouseDev = (NvOdmMouseDevice *)hDevice;

    MousePort = MOUSE_PS2_PORT_ID_0;
    count = CMD_MAX_RETRIES + 1;
    while ((ret==NV_FALSE) && (count--))
    {
        // fill up request structure
        Request.PacketType = NvEcPacketType_Request;
        Request.RequestType = NvEcRequestResponseType_AuxDevice;
        Request.RequestSubtype = 
            ((NvEcRequestResponseSubtype) 
             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID, MousePort))) |
             ((NvEcRequestResponseSubtype)NvEcAuxDeviceSubtype_SendCommand);
        Request.NumPayloadBytes = 2;
        Request.Payload[0] = 0xFF; // set the reset command
        Request.Payload[1] = 3;

        // Request to EC
        err = NvEcSendRequest(hMouseDev->hEc, &Request, 
	              &Response, sizeof(Request), sizeof(Response));
        if (NvSuccess != err)
        {
            //NVODMMOUSE_PRINTF(("NvEcSendRequest failed !!"));
            NvOsDebugPrintf("NvEcSendRequest failed !!\n");
            NvOsWaitUS(100000);
			continue;
        }

        // mouse not found
        if (NvEcStatus_Success != Response.Status)
        {
            //NVODMMOUSE_PRINTF(("EC response failed !!"));
            NvOsDebugPrintf("EC response failed !!\n");
            //if (MousePort != MOUSE_PS2_PORT_ID_1)
            //{
            //    count = CMD_MAX_RETRIES + 1;
            //    MousePort = MOUSE_PS2_PORT_ID_1;
            //}
            NvOsWaitUS(100000);
            continue;
        }

        if (Response.NumPayloadBytes != 3)
            continue;

        // success
        if (Response.Payload[0] == 0xFA)
        {
			ret = NV_TRUE; // at lease one Mouse found!
            hMouseDev->ValidMousePorts[i] = MousePort;
            //if (MousePort != MOUSE_PS2_PORT_ID_1)
            //{
            //    count = CMD_MAX_RETRIES + 1;
            //    MousePort = MOUSE_PS2_PORT_ID_1;
            //    i++;
            //    continue;
            //}
        }
	}
    
	return ret;
}