{ nvc4_grctx_init_tex_0 },
{ nvc0_grctx_init_wwdx_0 },
{ nvc0_grctx_init_mpc_0 },
{ nvc4_grctx_init_l1c_0 },
{ nvc0_grctx_init_tpccs_0 },
{ nvc4_grctx_init_sm_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc3),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_graph_context_ctor,
.dtor = nvc0_graph_context_dtor,
.init = _nouveau_graph_context_init,
.fini = _nouveau_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = nvc0_grctx_generate_main,
.unkn = nvc0_grctx_generate_unkn,
.hub = nvc0_grctx_pack_hub,
.gpc = nvc0_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvc4_grctx_pack_tpc,
.icmd = nvc0_grctx_pack_icmd,
.wr32 = _nouveau_gpuobj_wr32,
};
static struct nouveau_oclass
nv84_crypt_sclass[] = {
{ 0x74c1, &nv84_crypt_ofuncs },
{}
};
/*******************************************************************************
* PCRYPT context
******************************************************************************/
static struct nouveau_oclass
nv84_crypt_cclass = {
.handle = NV_ENGCTX(CRYPT, 0x84),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_engctx_ctor,
.dtor = _nouveau_engctx_dtor,
.init = _nouveau_engctx_init,
.fini = _nouveau_engctx_fini,
.rd32 = _nouveau_engctx_rd32,
.wr32 = _nouveau_engctx_wr32,
},
};
/*******************************************************************************
* PCRYPT engine/subdev functions
******************************************************************************/
static const struct nouveau_bitfield nv84_crypt_intr_mask[] = {
struct nvc0_graph_mthd
nvd9_grctx_init_mthd[] = {
{ 0x9097, nvc1_grctx_init_9097, },
{ 0x9197, nvc8_grctx_init_9197, },
{ 0x9297, nvc8_grctx_init_9297, },
{ 0x902d, nvc0_grctx_init_902d, },
{ 0x9039, nvc0_grctx_init_9039, },
{ 0x90c0, nvd9_grctx_init_90c0, },
{ 0x902d, nvd9_grctx_init_mthd_magic, },
{}
};
struct nouveau_oclass *
nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd9),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_graph_context_ctor,
.dtor = nvc0_graph_context_dtor,
.init = _nouveau_graph_context_init,
.fini = _nouveau_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = nvc0_grctx_generate_main,
.mods = nvc1_grctx_generate_mods,
.unkn = nvc1_grctx_generate_unkn,
.hub = nvd9_grctx_init_hub,
.gpc = nvd9_grctx_init_gpc,
.icmd = nvd9_grctx_init_icmd,
.mthd = nvd9_grctx_init_mthd,
nv_warn(parent, "[%s]\n", __PRETTY_FUNCTION__);
ret = nouveau_software_context_create(parent, engine, oclass, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
chan->base.vblank.channel = nv_gpuobj(parent->parent)->addr >> 12;
chan->base.vblank.event.func = nvc0_software_vblsem_release;
return 0;
}
static struct nouveau_oclass
nvc0_software_cclass = {
.handle = NV_ENGCTX(SW, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_software_context_ctor,
.dtor = _nouveau_software_context_dtor,
.init = _nouveau_software_context_init,
.fini = _nouveau_software_context_fini,
},
};
/*******************************************************************************
* software engine/subdev functions
******************************************************************************/
static int
nvc0_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
* VP object classes
******************************************************************************/
static struct nouveau_oclass
nv84_vp_sclass[] = {
{ 0x7476, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
* PVP context
******************************************************************************/
static struct nouveau_oclass
nv84_vp_cclass = {
.handle = NV_ENGCTX(VP, 0x84),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_xtensa_engctx_ctor,
.dtor = _nouveau_engctx_dtor,
.init = _nouveau_engctx_init,
.fini = _nouveau_engctx_fini,
.rd32 = _nouveau_engctx_rd32,
.wr32 = _nouveau_engctx_wr32,
},
};
/*******************************************************************************
* PVP engine/subdev functions
******************************************************************************/
static int
nve0_graph_sclass[] = {
{ 0x902d, &nouveau_object_ofuncs },
{ 0xa040, &nouveau_object_ofuncs },
{ 0xa097, &nouveau_object_ofuncs },
{ 0xa0c0, &nouveau_object_ofuncs },
{ 0xa0b5, &nouveau_object_ofuncs },
{}
};
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static struct nouveau_oclass
nve0_graph_cclass = {
.handle = NV_ENGCTX(GR, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_graph_context_ctor,
.dtor = nvc0_graph_context_dtor,
.init = _nouveau_graph_context_init,
.fini = _nouveau_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static void
int ret;
ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
priv->size, 0,
NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan));
return 0;
}
static struct nouveau_oclass
nv50_graph_cclass = {
.handle = NV_ENGCTX(GR, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_graph_context_ctor,
.dtor = _nouveau_graph_context_dtor,
.init = _nouveau_graph_context_init,
.fini = _nouveau_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static int
.wr32 = _nouveau_fifo_channel_wr32,
};
static struct nouveau_oclass
nv10_fifo_sclass[] = {
{ NV10_CHANNEL_DMA_CLASS, &nv10_fifo_ofuncs },
{}
};
/*******************************************************************************
* FIFO context - basically just the instmem reserved for the channel
******************************************************************************/
static struct nouveau_oclass
nv10_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0x10),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fifo_context_ctor,
.dtor = _nouveau_fifo_context_dtor,
.init = _nouveau_fifo_context_init,
.fini = _nouveau_fifo_context_fini,
.rd32 = _nouveau_fifo_context_rd32,
.wr32 = _nouveau_fifo_context_wr32,
},
};
/*******************************************************************************
* PFIFO engine
******************************************************************************/
static int
nv_wo32(chan, 0x3450, 0x3f800000);
nv_wo32(chan, 0x380c, 0x3f800000);
nv_wo32(chan, 0x3820, 0x3f800000);
nv_wo32(chan, 0x384c, 0x40000000);
nv_wo32(chan, 0x3850, 0x3f800000);
nv_wo32(chan, 0x3854, 0x3f000000);
nv_wo32(chan, 0x385c, 0x40000000);
nv_wo32(chan, 0x3860, 0x3f800000);
nv_wo32(chan, 0x3868, 0xbf800000);
nv_wo32(chan, 0x3870, 0xbf800000);
return 0;
}
static struct nvkm_oclass
nv35_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x35),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv35_gr_context_ctor,
.dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static int
.wr32 = _nvkm_gpuobj_wr32,
};
static struct nvkm_oclass
g84_cipher_sclass[] = {
{ 0x74c1, &g84_cipher_ofuncs },
{}
};
/*******************************************************************************
* PCIPHER context
******************************************************************************/
static struct nvkm_oclass
g84_cipher_cclass = {
.handle = NV_ENGCTX(CIPHER, 0x84),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_engctx_ctor,
.dtor = _nvkm_engctx_dtor,
.init = _nvkm_engctx_init,
.fini = _nvkm_engctx_fini,
.rd32 = _nvkm_engctx_rd32,
.wr32 = _nvkm_engctx_wr32,
},
};
/*******************************************************************************
* PCIPHER engine/subdev functions
******************************************************************************/
static const struct nvkm_bitfield
nv_wo32(chan, 0x344c, 0x3f800000);
nv_wo32(chan, 0x3808, 0x3f800000);
nv_wo32(chan, 0x381c, 0x3f800000);
nv_wo32(chan, 0x3848, 0x40000000);
nv_wo32(chan, 0x384c, 0x3f800000);
nv_wo32(chan, 0x3850, 0x3f000000);
nv_wo32(chan, 0x3858, 0x40000000);
nv_wo32(chan, 0x385c, 0x3f800000);
nv_wo32(chan, 0x3864, 0xbf800000);
nv_wo32(chan, 0x386c, 0xbf800000);
return 0;
}
static struct nouveau_oclass
nv30_graph_cclass = {
.handle = NV_ENGCTX(GR, 0x30),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv30_graph_context_ctor,
.dtor = _nouveau_graph_context_dtor,
.init = nv20_graph_context_init,
.fini = nv20_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static int
if (ret)
return ret;
return 0;
}
static int
nv98_ppp_context_fini(struct nouveau_object *object, bool suspend)
{
struct nv98_ppp_chan *priv = (void *)object;
return nouveau_ppp_context_fini(&priv->base, suspend);
}
static struct nouveau_oclass
nv98_ppp_cclass = {
.handle = NV_ENGCTX(PPP, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv98_ppp_context_ctor,
.dtor = nv98_ppp_context_dtor,
.init = nv98_ppp_context_init,
.fini = nv98_ppp_context_fini,
.rd32 = _nouveau_ppp_context_rd32,
.wr32 = _nouveau_ppp_context_wr32,
},
};
/*******************************************************************************
* PPPP engine/subdev functions
******************************************************************************/
static void
nv_wo32(chan, 0x26e4, 0x3f000000);
nv_wo32(chan, 0x26ec, 0x40000000);
nv_wo32(chan, 0x26f0, 0x3f800000);
nv_wo32(chan, 0x26f8, 0xbf800000);
nv_wo32(chan, 0x2700, 0xbf800000);
nv_wo32(chan, 0x3024, 0x000fe000);
nv_wo32(chan, 0x30a0, 0x000003f8);
nv_wo32(chan, 0x33fc, 0x002fe000);
for (i = 0x341c; i <= 0x3438; i += 4)
nv_wo32(chan, i, 0x001c527c);
return 0;
}
static struct nouveau_oclass
nv2a_graph_cclass = {
.handle = NV_ENGCTX(GR, 0x2a),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv2a_graph_context_ctor,
.dtor = _nouveau_graph_context_dtor,
.init = nv20_graph_context_init,
.fini = nv20_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static int
nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
}
nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
nvc0_graph_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
nvc0_graph_mthd(priv, oclass->mthd);
nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
nv_mask(priv, 0x41be10, 0x00800000, 0x00800000);
}
struct nouveau_oclass *
nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xe4),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_graph_context_ctor,
.dtor = nvc0_graph_context_dtor,
.init = _nouveau_graph_context_init,
.fini = _nouveau_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
.hub = nve4_grctx_pack_hub,
.gpc = nve4_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nve4_grctx_pack_tpc,
.ppc = nve4_grctx_pack_ppc,
gk110b_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ nvf0_grctx_init_tex_0 },
{ nvf0_grctx_init_mpc_0 },
{ nvf0_grctx_init_l1c_0 },
{ gk110b_grctx_init_sm_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xf1),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_graph_context_ctor,
.dtor = nvc0_graph_context_dtor,
.init = _nouveau_graph_context_init,
.fini = _nouveau_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
.hub = nvf0_grctx_pack_hub,
.gpc = nvf0_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = gk110b_grctx_pack_tpc,
.ppc = nvf0_grctx_pack_ppc,
nv_wo32(chan, 0x274c, 0x3f000000);
nv_wo32(chan, 0x2754, 0x40000000);
nv_wo32(chan, 0x2758, 0x3f800000);
nv_wo32(chan, 0x2760, 0xbf800000);
nv_wo32(chan, 0x2768, 0xbf800000);
nv_wo32(chan, 0x308c, 0x000fe000);
nv_wo32(chan, 0x3108, 0x000003f8);
nv_wo32(chan, 0x3468, 0x002fe000);
for (i = 0x3484; i <= 0x34a0; i += 4)
nv_wo32(chan, i, 0x001c527c);
return 0;
}
static struct nouveau_oclass
nv25_graph_cclass = {
.handle = NV_ENGCTX(GR, 0x25),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv25_graph_context_ctor,
.dtor = _nouveau_graph_context_dtor,
.init = nv20_graph_context_init,
.fini = nv20_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static int
nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
}
nvc0_graph_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
nvc0_graph_mthd(priv, oclass->mthd);
nv_mask(priv, 0x419e00, 0x00808080, 0x00808080);
nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000);
nv_mask(priv, 0x419f80, 0x80000000, 0x80000000);
nv_mask(priv, 0x419f88, 0x80000000, 0x80000000);
}
struct nouveau_oclass *
gm107_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0x08),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_graph_context_ctor,
.dtor = nvc0_graph_context_dtor,
.init = _nouveau_graph_context_init,
.fini = _nouveau_graph_context_fini,
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = gm107_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
.hub = gm107_grctx_pack_hub,
.gpc = gm107_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = gm107_grctx_pack_tpc,
.ppc = gm107_grctx_pack_ppc,
struct nvkm_object **pobject)
{
struct nv04_sw_chan *chan;
int ret;
ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
return 0;
}
static struct nvkm_oclass
nv04_sw_cclass = {
.handle = NV_ENGCTX(SW, 0x04),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_sw_context_ctor,
.dtor = _nvkm_sw_context_dtor,
.init = _nvkm_sw_context_init,
.fini = _nvkm_sw_context_fini,
},
};
/*******************************************************************************
* software engine/subdev functions
******************************************************************************/
void
nv04_sw_intr(struct nvkm_subdev *subdev)
{
ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4,
0, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
nv_wo32(chan, 0x0070, 0x00801ec1);
nv_wo32(chan, 0x007c, 0x0000037c);
bar->flush(bar);
return 0;
}
static struct nvkm_oclass
nv50_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x50),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_mpeg_context_ctor,
.dtor = _nvkm_mpeg_context_dtor,
.init = _nvkm_mpeg_context_init,
.fini = _nvkm_mpeg_context_fini,
.rd32 = _nvkm_mpeg_context_rd32,
.wr32 = _nvkm_mpeg_context_wr32,
},
};
/*******************************************************************************
* PMPEG engine/subdev functions
******************************************************************************/
void
/* allocate display hardware to client */
mutex_lock(&nv_subdev(priv)->mutex);
if (list_empty(&nv_engine(priv)->contexts)) {
ret = nouveau_engctx_create(parent, engine, oclass, NULL,
0x10000, 0x10000,
NVOBJ_FLAG_HEAP, &ectx);
*pobject = nv_object(ectx);
}
mutex_unlock(&nv_subdev(priv)->mutex);
return ret;
}
struct nouveau_oclass
nv50_disp_cclass = {
.handle = NV_ENGCTX(DISP, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_disp_data_ctor,
.dtor = _nouveau_engctx_dtor,
.init = _nouveau_engctx_init,
.fini = _nouveau_engctx_fini,
.rd32 = _nouveau_engctx_rd32,
.wr32 = _nouveau_engctx_wr32,
},
};
/*******************************************************************************
* Display engine implementation
******************************************************************************/
static const struct nouveau_enum
return -ENOMEM;
for (i = 0; i < chan->vblank.nr_event; i++) {
ret = nouveau_event_new(pdisp->vblank, i, pclass->vblank,
chan, &chan->vblank.event[i]);
if (ret)
return ret;
}
chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12;
return 0;
}
static struct nv50_software_cclass
nv50_software_cclass = {
.base.handle = NV_ENGCTX(SW, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_software_context_ctor,
.dtor = _nouveau_software_context_dtor,
.init = _nouveau_software_context_init,
.fini = _nouveau_software_context_fini,
},
.vblank = nv50_software_vblsem_release,
};
/*******************************************************************************
* software engine/subdev functions
******************************************************************************/
int
nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
