void* NV_API_CALL nv_i2c_add_adapter(nv_state_t *nv, NvU32 port)
{
RM_STATUS rmStatus;
nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv);
struct i2c_adapter *pI2cAdapter = NULL;
int osstatus = 0;
#if defined(KERNEL_2_4)
if (!NV_WEAK_SYMBOL_PRESENT(i2c_add_adapter))
return NULL;
if (!NV_WEAK_SYMBOL_PRESENT(i2c_del_adapter))
return NULL;
#endif
// get a i2c adapter
rmStatus = os_alloc_mem((void **)&pI2cAdapter,sizeof(struct i2c_adapter));
if (rmStatus != RM_OK)
return NULL;
// fill in with default structure
os_mem_copy((void *)pI2cAdapter, (void *)&nv_i2c_adapter_prototype, sizeof(struct i2c_adapter));
#if !defined(KERNEL_2_4)
pI2cAdapter->dev.parent = &nvl->dev->dev;
#endif
snprintf(pI2cAdapter->name, I2C_NAME_SIZE,
"NVIDIA i2c adapter %u at %x:%02x.%u", port, nv->bus,
nv->slot, PCI_FUNC(nvl->dev->devfn));
// add our data to the structure
pI2cAdapter->algo_data = (void *)nv;
// attempt to register with the kernel
osstatus = i2c_add_adapter(pI2cAdapter);
if (osstatus)
{
// free the memory and NULL the ptr
os_free_mem(pI2cAdapter);
pI2cAdapter = NULL;
}
return ((void *)pI2cAdapter);
}
NvBool nv_get_rsync_relaxed_ordering_mode(
nv_state_t *nv
)
{
nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv);
/* shouldn't be called without opening a device */
WARN_ON(NV_ATOMIC_READ(nvl->usage_count) == 0);
/*
* g_rsync_info.relaxed_ordering_mode can be safely accessed outside of
* g_rsync_info.lock once a device is opened. During nvidia_open(), we
* lock the relaxed ordering state by ref-counting the rsync module
* through get_relaxed_ordering_mode.
*/
return g_rsync_info.relaxed_ordering_mode;
}
RM_STATUS KernAllocAGPPages(
nv_stack_t *sp,
nv_state_t *nv,
NvU32 PageCount,
void **pPriv_data,
NvU32 *Offset
)
{
#ifndef AGPGART
return RM_ERROR;
#else
nv_linux_state_t *nvl;
agp_memory *ptr;
nvl = NV_GET_NVL_FROM_NV_STATE(nv);
if (rm_alloc_agp_bitmap(sp, nv, PageCount, Offset))
{
nv_printf(NV_DBG_INFO, "NVRM: AGPGART: failed to allocate AGP offset\n");
return RM_ERROR;
}
ptr = NV_AGPGART_ALLOCATE_MEMORY(drm_agp_p, nvl->agp_bridge,
PageCount, AGP_NORMAL_MEMORY);
if (ptr == NULL)
{
nv_printf(NV_DBG_ERRORS, "NVRM: AGPGART: no pages available\n");
rm_free_agp_bitmap(sp, nv, PageCount, *Offset);
return RM_ERR_NO_FREE_MEM;
}
if (NV_AGPGART_BIND_MEMORY(drm_agp_p, ptr, *Offset))
{
nv_printf(NV_DBG_INFO, "NVRM: AGPGART: unable to bind %u pages\n", PageCount);
NV_AGPGART_FREE_MEMORY(drm_agp_p, ptr);
rm_free_agp_bitmap(sp, nv, PageCount, *Offset);
return RM_ERROR;
}
*pPriv_data = (void *)ptr;
return RM_OK;
#endif /* AGPGART */
}
void nv_wait_for_rsync(
nv_state_t *nv
)
{
nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv);
/* shouldn't be called without opening a device */
WARN_ON(NV_ATOMIC_READ(nvl->usage_count) == 0);
/*
* g_rsync_info.relaxed_ordering_mode can be safely accessed outside of
* g_rsync_info.lock once a device is opened. During nvidia_open(), we
* block unregistration of the rsync driver by ref-counting the module
* through get_relaxed_ordering_mode.
*/
if (g_rsync_info.relaxed_ordering_mode)
{
WARN_ON(g_rsync_info.wait_for_rsync == NULL);
g_rsync_info.wait_for_rsync(nvl->dev, g_rsync_info.data);
}
}
RM_STATUS KernTeardownAGP(
nv_stack_t *sp,
nv_state_t *nv
)
{
#ifndef AGPGART
return RM_ERROR;
#else
RM_STATUS status;
nv_linux_state_t *nvl;
void *bitmap;
nvl = NV_GET_NVL_FROM_NV_STATE(nv);
#ifdef CONFIG_MTRR
if (nv_pat_mode == NV_PAT_MODE_DISABLED)
mtrr_del(-1, nv->agp.address, nv->agp.size);
#endif
NV_AGPGART_BACKEND_RELEASE(drm_agp_p, nvl->agp_bridge);
#if defined(KERNEL_2_4)
inter_module_put("drm_agp");
#endif
status = rm_clear_agp_bitmap(sp, nv, &bitmap);
if (status != RM_OK)
{
nv_printf(NV_DBG_WARNINGS, "NVRM: AGPGART: failed to clear bitmap\n");
return status;
}
os_free_mem(bitmap);
return RM_OK;
#endif /* AGPGART */
}
RM_STATUS KernInitAGP(
nv_stack_t *sp,
nv_state_t *nv,
NvU64 *ap_phys_base,
NvU64 *ap_limit
)
{
#ifndef AGPGART
return RM_ERROR;
#else
RM_STATUS status = RM_ERROR;
nv_linux_state_t *nvl;
void *bitmap;
agp_kern_info agp_info;
NvU32 bitmap_size;
NvU32 agp_rate = (8 | 4 | 2 | 1);
NvU32 enable_sba = 0;
NvU32 enable_fw = 0;
NvU32 agp_mode = 0;
#if defined(KERNEL_2_4)
if (!(drm_agp_p = inter_module_get_request("drm_agp", "agpgart")))
return RM_ERR_NOT_SUPPORTED;
#endif
/* NOTE: from here down, return an error code of '-1'
* that indicates that agpgart is loaded, but we failed to use it
* in some way. This is so we don't try to use nvagp and lock up
* the memory controller.
*/
nvl = NV_GET_NVL_FROM_NV_STATE(nv);
if (NV_AGPGART_BACKEND_ACQUIRE(drm_agp_p, nvl->agp_bridge, nvl->dev))
{
nv_printf(NV_DBG_INFO, "NVRM: AGPGART: no backend available\n");
status = RM_ERR_NOT_SUPPORTED;
goto bailout;
}
if (NV_AGPGART_COPY_INFO(drm_agp_p, nvl->agp_bridge, &agp_info))
{
nv_printf(NV_DBG_ERRORS,
"NVRM: AGPGART: kernel reports chipset as unsupported\n");
goto release;
}
if (nv_pat_mode == NV_PAT_MODE_DISABLED)
{
#ifdef CONFIG_MTRR
/*
* Failure to set a write-combining range on the AGP aperture may
* be due to the presence of other memory ranges with conflicting
* caching attributes. Play safe and fail AGP initialization.
*/
if (mtrr_add(agp_info.aper_base, agp_info.aper_size << 20,
MTRR_TYPE_WRCOMB, 0) < 0)
#endif
{
nv_printf(NV_DBG_ERRORS,
"NVRM: AGPGART: unable to set MTRR write-combining\n");
goto release;
}
}
// allocate and set the bitmap for tracking agp allocations
bitmap_size = (agp_info.aper_size << 20)/PAGE_SIZE/8;
if (os_alloc_mem(&bitmap, bitmap_size))
{
nv_printf(NV_DBG_ERRORS, "NVRM: AGPGART: unable to allocate bitmap\n");
goto failed;
}
os_mem_set(bitmap, 0xff, bitmap_size);
status = rm_set_agp_bitmap(sp, nv, bitmap);
if (status != RM_OK)
{
nv_printf(NV_DBG_ERRORS, "NVRM: AGPGART: unable to set bitmap\n");
os_free_mem(bitmap);
goto failed;
}
agp_mode = agp_info.mode;
rm_read_registry_dword(sp, NULL, "NVreg", "ReqAGPRate", &agp_rate);
agp_mode = NV_AGPGART_MODE_BITS_RATE(agp_mode, agp_rate);
agp_mode |= 1; /* avoid 0x mode request */
if (agp_mode & 2) agp_mode &= ~1;
if (agp_mode & 4) agp_mode &= ~2;
rm_read_registry_dword(sp, NULL, "NVreg", "EnableAGPSBA", &enable_sba);
agp_mode |= NV_AGPGART_MODE_BITS_SBA(enable_sba);
rm_read_registry_dword(sp, NULL, "NVreg", "EnableAGPFW", &enable_fw);
agp_mode |= NV_AGPGART_MODE_BITS_FW(enable_fw);
agp_info.mode &= (0xff000000 | agp_mode);
NV_AGPGART_BACKEND_ENABLE(drm_agp_p, nvl->agp_bridge, agp_info.mode);
*ap_phys_base = (unsigned)agp_info.aper_base;
*ap_limit = (unsigned)((agp_info.aper_size << 20) - 1);
return RM_OK;
failed:
#ifdef CONFIG_MTRR
if (nv_pat_mode == NV_PAT_MODE_DISABLED)
mtrr_del(-1, agp_info.aper_base, agp_info.aper_size << 20);
#endif
release:
NV_AGPGART_BACKEND_RELEASE(drm_agp_p, nvl->agp_bridge);
bailout:
#if defined(KERNEL_2_4)
inter_module_put("drm_agp");
#endif
return status;
#endif /* AGPGART */
}
extern char *NVreg_AssignGpus;
static char nv_registry_keys[NV_MAX_REGISTRY_KEYS_LENGTH];
static int nv_procfs_read_registry(struct seq_file *s, void *v);
#define NV_PROC_WRITE_BUFFER_SIZE (64 * PAGE_SIZE)
static int
nv_procfs_read_gpu_info(
struct seq_file *s,
void *v
)
{
nv_state_t *nv = s->private;
nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv);
struct pci_dev *dev = nvl->dev;
char *type, *fmt, tmpstr[NV_DEVICE_NAME_LENGTH];
int status;
NvU8 *uuid;
NvU32 vbios_rev1, vbios_rev2, vbios_rev3, vbios_rev4, vbios_rev5;
NvU32 fpga_rev1, fpga_rev2, fpga_rev3;
nv_stack_t *sp = NULL;
NV_KMEM_CACHE_ALLOC_STACK(sp);
if (sp == NULL)
{
nv_printf(NV_DBG_ERRORS, "NVRM: failed to allocate stack!\n");
return 0;
}