/**
* Request boot up voltage
*
*
*
* @param[in] LinkCap Global GEN capability
* @param[in] Pcie Pointer to PCIe configuration data area
*/
VOID
PcieFmSetBootUpVoltage (
IN PCIE_LINK_SPEED_CAP LinkCap,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
FCRxFE00_70A2_STRUCT FCRxFE00_70A2;
D18F3x15C_STRUCT D18F3x15C;
UINT8 TargetVidIndex;
UINT32 Temp;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Enter\n");
ASSERT (LinkCap <= PcieGen2);
GnbLibPciRead (
MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
AccessWidth32,
&D18F3x15C.Value,
GnbLibGetHeader (Pcie)
);
Temp = D18F3x15C.Value;
if (LinkCap > PcieGen1) {
FCRxFE00_70A2.Value = NbSmuReadEfuse (FCRxFE00_70A2_ADDRESS, GnbLibGetHeader (Pcie));
TargetVidIndex = (UINT8) FCRxFE00_70A2.Field.PcieGen2Vid;
} else {
TargetVidIndex = PcieSiliconGetGen1VoltageIndex (GnbLibGetHeader (Pcie));
}
IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid Index %d\n", LinkCap, TargetVidIndex);
if (TargetVidIndex == 3) {
D18F3x15C.Field.SclkVidLevel2 = D18F3x15C.Field.SclkVidLevel3;
GnbLibPciWrite (
MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
AccessWidth32,
&D18F3x15C.Value,
GnbLibGetHeader (Pcie)
);
PcieSiliconRequestVoltage (2, GnbLibGetHeader (Pcie));
}
GnbLibPciWrite (
MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
AccessWidth32,
&Temp,
GnbLibGetHeader (Pcie)
);
PcieSiliconRequestVoltage (TargetVidIndex, GnbLibGetHeader (Pcie));
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Exit\n");
}
/**
* Family 14h core 0 entry point for performing power plane initialization.
*
* The steps are as follows:
* 1. BIOS must initialize D18F3xD8[VSRampSlamTime].
* 2. BIOS must configure D18F3xA0[PsiVidEn & PsiVid] and
* D18F3x128[NbPsiVidEn & NbPsiVid].
* 3. BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1.
* BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid].
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14PmPwrPlaneInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 SystemSlewRate;
UINT32 PciRegister;
UINT32 WaitTime;
UINT32 VSRampSlamTime;
PCI_ADDR PciAddress;
FCRxFE00_6000_STRUCT FCRxFE00_6000;
// Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements.
// Voltage Ramp Time = maximum time to change voltage by 12.5mV rounded to the next higher encoding.
SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <=
CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ?
CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate :
CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate;
ASSERT (SystemSlewRate != 0);
// First, calculate the time it takes to change 12.5mV using the VRM slew rate.
WaitTime = (12500 * 100) / SystemSlewRate;
if (((12500 * 100) % SystemSlewRate) != 0) {
WaitTime++;
}
// Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds
// to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable
// VRM can be.
for (VSRampSlamTime = ((sizeof (F14VSRampSlamWaitTimes) / sizeof (F14VSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) {
if (WaitTime <= F14VSRampSlamWaitTimes[VSRampSlamTime]) {
break;
}
}
if (WaitTime > F14VSRampSlamWaitTimes[0]) {
// The VRMs on this motherboard are too slow for this CPU.
IDS_ERROR_TRAP;
}
// Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
PciAddress.AddressValue = CPTC1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSRampSlamTime = VSRampSlamTime;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
// Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid].
F14PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
// Step 3 - Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1.
// Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid].
FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader);
F14EarlySampleCoreSupport.F14PowerPlaneInitHook (&FCRxFE00_6000, StdHeader);
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
